Motorola MVME1X7P User Manual
Page 313
IN-11
I
N
D
E
X
SCC Receive Interrupt Control register
(PCCchip2 ASIC)
SCC Transmit Interrupt Control register
scrub cycle type
SCSI
controller interface (PCCchip2 ASIC)
Error Status register (PCCchip2 ASIC)
interface
Interrupt Control register (PCCchip2
memory map
offboard error
parity error
terminator configuration
SDRAM
implementation
,
,
map decoder
segment size, address translation
segment size, translating
SERCLK driver
serial
interface description
port connection diagrams
short I/O area, VMEchip2 ASIC
short I/O map decoder (VMEbus)
short I/O memory map
short I/O segment, VMEbus
short I/O space, VMEbus
signal interrupts SIG0-SIG3 (VMEchip2
Single (SGL) arbitration mode, VMEbus
single bit error
size, VMEbus segment
,
slave map decoders, VMEbus
snoop control
snoop control bits
snoop control, LANC bus error
,
snoop signal lines (DMAC)
software 7-0 interrupters, VMEbus
software interrupts
specifications
applicable industry standards
SRAM (static RAM)
specifications
standard access cycles, VMEbus
starting address register (VMEbus slave)
starting address register, slave map decoder
static RAM (SRAM)
status LEDs
status register, MPU (DMAC)
strobe timing
strobe, printer
supervisor address modifier code (VMEbus)
Supervisor Stack pointer (on MVME177)
supervisory access cycles, VMEbus
switches (ABORT and RESET)
syndrome decoding
SYSFAIL* interrupter
SYSFAIL* signal line
,
SYSRESET function, VMEchip2 ASIC
,
system controller function, VMEchip2 ASIC
enable/disable