NEC PD75402A - Manual (Page 25)

CHAPTER 2. PIN FUNCTIONS
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2.2.2 P20 to P23 (Port 2) ..... PCL Dual-Function 3-Stae Input/Otput
P30 to P33 (Port 3) ..... 3-State Input/Output
P50 to P53 (Port 5) ..... N-ch Open Drain Middle-Voltage (10 V) Input/Output
P60 to P63 (Port 6) ..... 3-State Input/Output
The 4-bit input/output port with the output latch: Port 2’s, 3’s, 5’s, 6’s 4-bit input/output pins. Port 2 also shares
the programmable clock output (PCL) function with P22 in addition to having the input/output port function. Port
5 has the N-ch open drain middle-voltage (10 V) output.
Port 3 allows to designate input/output bit-wise using the port mode register (PMGA). Ports 2, 5 and 6 allow to
designate input/output in 4-bit units using the port mode register (PMGA, PMGB).
Ports 2, 3 and 6 allow to designate to build in the pull-up resistor by software in 4-bit units. Such designation
is made using the pull-up resistor designation register (POGA).
The
µ
PD75402A’s Port 5 allows to designate to build in the pull-up resistor by mask option bit-wise. The
µ
PD75P402’s Port 5 cannot be built in with the pull-up resistor. Ports 3, 5 and 6 have large-current output and can
drive the LED directly.
Ports 2, 3 and 6 turn input ports (output high impedance) at RESET input. Port 5 turns high level (if built in with
the pull-up resistor) or high impedance. The content of the output latch turns indeterminate.
2.2.3 SCK, SO/SB0, SI ..... Port 0 Dual-Function 3-State Input/Output
A serial interface input/output pin. It operates according to the serial operating mode register (CSIM) setting.
Each has Schmitt-triggered input.
The serial interface stops at RESET input and each turns into an input port.
2.2.4 INT0 ..... Port 1 Dual-Function Input
An external interrupt request input pin. It is designatable for either of the 3 of rising edge detection, falling edge
detection and rising and falling edge detection using the external interrupt mode register (IM0).
INT0 has Schmitt-triggered input and is built in with the noise eliminator by the sampling clock.
2.2.5 INT2 ..... Port 1 Dual-Function Input
An external test input pin. The detected edge is fixed to the rising edge. It has Schmitt-triggered input and is built
in with the noise eliminator by analog delay.
INT2 has asynchronous input. It accepts a signal having a certain high-level width irrespective of the CPU’s
operation clock if one is input.
2.2.6 PCL ..... Port 2 Dual-Function Output
A programmable clock output pin. It is used to supply the clock to the peripheral LSI. The PCL output is also
applicable to the remote control carrier signal.
The clock output function stops at RESET input and PCL turns into an input port (P22).