NEC PD75402A - Manual (Page 63)

52
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
Fig. 5-7 Format of Pull-Up Resistor Specification Register
Address 7 6 5 4 3 2 1 0 Symbol
FDCH – PO6 – – PO3 PO2 PO1 PO0 POGA
Port 0 (P01 to P03)
Port 1 (P12)
Port 2 (P20 to P23)
Port 3 (P30 to P33)
Port 6 (P60 to P63)
Specification
0 Pull-up resistor not incorporated
1 Pull-up resistor incorporated
The timing for switching of pull-up resistor presence/ absence by the setting of the pull-up resistor specification
register (POGA) is shown in Fig. 5-8.
Fig. 5-8 Pull-Up Resistor Incorporation Switching Timing
Remarks
Φ
o
through
Φ
3
are internal operation timing clock pulses.
After pull-up resistor incorporation has been specified by overwriting POGA, in consideration of the external load
capacity the pin level should be stabilized by execution of an NOP instruction etc. before an input/output instruction
is executed.
Example To perform input after specifying incorporation of a pull-up resistor in port 1.
MOV XA, #02H ; Pull-up resistor incorporated in port 1
MOV POGA, XA
Wait until pin level is stabilized in consideration of
external load capacity.
IN A, PORT1
……
Instruction
Execution
POGA
3 1
2-Machine Cycles
Manipulation Instruction
Φ Φ Φ Φ
0