Chapter 2 – Texas Instruments MSP50C614 User Manual
Page 31
2-1
MSP50C614 Architecture
A detailed description of MSP50C614 architecture is included in this chapter.
After reading this chapter, the reader will have in-depth knowledge of internal
blocks, memory organization, interrupt system, timers, clock control mecha-
nism, and various low power modes.
Topic
Page
2.1
Architecture Overview
2–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Computation Unit
2–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Data Memory Address Unit
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Program Counter Unit
2–14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Bit Logic Unit
2–14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Memory Organization: RAM and ROM
2–15
. . . . . . . . . . . . . . . . . . . . . . . .
2.7
Interrupt Logic
2–22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8
Timer Registers
2–26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9
Clock Control
2–29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Execution Timing
2–33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Reduced Power Modes
2–34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2