Table 2. common clock frequencies, Table 3. mclk dividers, Table 3. slave mode mclk dividers – Cirrus Logic CS4245 User Manual
Page 31: Table 2, Cs4245
DS656F3
31
CS4245
in Master Mode, and receive the proper clocks in Slave Mode.
illustrates several standard audio
sample rates and the required MCLK and LRCK frequencies.
In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK
ratio to achieve a post-divider MCLK/LRCK ratio of 256x for SSM, 128x for DSM, or 64x for QSM.
Table 3
lists the appropriate dividers.
LRCK
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
384x
512x
768x
1024x
32
-
-
-
-
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
-
-
-
-
11.2896
16.9344
22.5792
33.8680
45.1584
48
-
-
-
-
12.2880
18.4320
24.5760
36.8640
49.1520
64
-
-
8.1920
12.2880
16.3840
24.5760
32.7680
-
-
88.2
-
-
11.2896
16.9344
22.5792
33.8680
45.1584
-
-
96
-
-
12.2880
18.4320
24.5760
36.8640
49.1520
-
-
128
8.1920
12.2880
16.3840
24.5760
32.7680
-
-
-
-
176.4
11.2896
16.9344
22.5792
33.8680
45.1584
-
-
-
-
192
12.2880
18.4320
24.5760
36.8640
49.1520
-
-
-
-
Mode
QSM
DSM
SSM
Table 2. Common Clock Frequencies
MCLK/LRCK Ratio
MCLK Dividers
64x
-
-
÷1
96x
-
-
÷1.5
128x
-
ч1
ч2
192x
-
ч1.5
ч3
256x
ч1
ч2
ч4
384x
ч1.5
ч3
-
512x
ч2
ч4
-
768x
÷3
-
-
1024x
÷4
-
-
Mode
SSM
DSM
QSM
Table 3. MCLK Dividers