Cirrus Logic CS4245 - Manual (Page 50)

50 DS656F3
CS4245
6.12.3 Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INT pin functions as an active low open drain driver and will require an exter-
nal pull-up resistor for proper operation.
6.13 Interrupt Status - Address 0Dh
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Status bits that are masked off in the associated mask register will always be ‘0’ in
this register. This register defaults to 00h.
6.13.1 ADC Clock Error (Bit 3)
Function:
Indicates the occurrence of an ADC clock error condition.
6.13.2 DAC Clock Error (Bit 2)
Function:
Indicates the occurrence of a DAC clock error condition.
6.13.3 ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4 ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
6.14 Interrupt Mask - Address 0Eh
Function:
The bits of this register serve as a mask for the Status sources found in the register “Interrupt Status - Ad-
dress 0Dh” on page 50 . If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect
the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence
will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Sta-
tus register.
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved ADCClkErr DACClkErr ADCOvfl ADCUndrfl
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved ADCClkErrM DACClkErrM ADCOvflM ADCUndrflM