2 master clock 2 frequency (bits 2:0), Table 13. mclk 2 frequency, 6 signal selection - address 06h – Cirrus Logic CS4245 User Manual
Page 46: 1 auxiliary output source select (bits 6:5), Table 14. auxiliary output source selection, 2 digital loopback (bit 1), 3 asynchronous mode (bit 0), Section 6.6.1, Cs4245
46
DS656F3
CS4245
6.5.2
Master Clock 2 Frequency (Bits 2:0)
Function:
These bits set the frequency of the supplied MCLK2 signal. See
for the appropriate settings.
6.6
Signal Selection - Address 06h
6.6.1
Auxiliary Output Source Select (Bits 6:5)
Function:
These bits are used to select the analog output source. Please refer to
6.6.2
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC are enabled. Please refer to
“Internal Digital Loopback” on page 36
.
6.6.3
Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent asynchronous sample rates de-
rived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at synchronous
sample rates derived from MCLK1.
MCLK2 Divider
MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0
ч 1
0
0
0
ч 1.5
0
0
1
ч 2
0
1
0
ч 3
0
1
1
ч 4
1
0
0
Reserved
1
0
1
Reserved
1
1
x
Table 13. MCLK 2 Frequency
7
6
5
4
3
2
1
0
Reserved
AOutSel1
AOutSel0
Reserved
Reserved
Reserved
LOOP
ASynch
AOutSel1
AOutSel0
Auxiliary Output Source
0
0
High Impedance
0
1
DAC Output
1
0
PGA Output
1
1
Reserved
Table 14. Auxiliary Output Source Selection