Altera Interlaken MegaCore Function - Manual (Page 63)

June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
6. Qsys Design Examples
Design Examples Overview
The Interlaken MegaCore function includes four demonstration design examples.
Each license allows you to program a Stratix IV device with one of the four design
examples.
Table 6–1 lists the design example available for each license. The design
example names specify the Interlaken MegaCore function variations they test.
For information about acquiring the license required to program each design example
variation, refer to
“Installation and Licensing” on page 1–4 .
Figure 6–1 shows a block diagram correct for each design example.
The design examples each demonstrate a system that combines an Interlaken
MegaCore function with two channel clients that generate input to the application
interface and check the resulting output. The Interlaken link transmit lines are
connected to the receive lines, creating an external feedback loop. From the Qsys
system provided with each design example, Qsys automatically generates Verilog
HDL files that include all the required components and interconnections. Qsys also
generates IEEE encrypted functional simulation models for some third-party
simulation tools, as described in
“Simulating the System” on page 2–6 . The Verilog
HDL files that Qsys generates are ready to be compiled in the Quartus II software for
programming an Altera device.
Table 6–1. Interlaken MegaCore Function Design Examples
License Design Example
IP-INTLKN/20G/4L alt_interlaken_4lane_3g
IP-INTLKN/40G/8L alt_interlaken_8lane_6g
IP-INTLKN/100G/12L alt_interlaken_12lane_10g
IP-INTLKN/100G/20L alt_interlaken_20lane_6g
Figure 6–1. Qsys Interlaken Design Example
Interlaken
Channel 0
Client
Interlaken
Channel 1
Client
Testbench Glue Logic
Qsys System
Quartus II Project
Interlaken
MegaCore Function
Avalon Streaming Connection Avalon Streaming Connection
Transceiver Banks