Altera Interlaken MegaCore Function - Manual (Page 77)

Appendix B: Excluding Transceivers for Faster Simulation B–5
External Transceiver Interface Data and Clock Signals
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
External Transceiver Interface Data and Clock Signals
If you turn on Exclude transceivers, your Interlaken MegaCore function does not
include high-speed transceivers. In that case, the data for the Interlaken link appears
on the external transceiver interface.
Table B–1 lists the external transceiver interface
data and clock signals in Interlaken MegaCore function variations that do not include
high-speed transceivers.
Table B–1. External Transceiver Interface Signals (Part 1 of 2)
Signal Direction Description
tx_dataN_export[S:0]
Parallel transmit data interface. N = 0 for 4-lane variations; N = {0,1} for 8- and
10-lane variations, N = {0,1,2} for 12-lane variations, and N = {0,1,2,3} for
20-lane variations.
The width of the port for each value of N is the transceiver datapath width
times the number of channels used on an Altera device transceiver in
variations that include the transceivers. For the 12-lane, 10-Gbps variation,
the transceiver datapath width is 40. For all the other variations, the
transceiver datapath width is 20. The number of channels is 4 for 4-, 8-, and
12-lane variations, and 5 for 10- and 20-lane variations. (S = calculated port
width – 1).
Lane 0 holds the MSB of the output data, which is output on
tx_dataN_export
with the highest value of N. Refer to Figure 4–2 on
page 4–6 through Figure 4–6 on page 4–9 , ignoring the transceivers in the
figures.
In an 8-lane variation, lane 0 is output on tx_data1_export[79:60],
lane 1 is output on tx_data1_export[59:40], and so on;
lane 5 is output on tx_data0_export[59:40],
lane 6 is output on tx_data0_export[39:20], and
lane 7 is output on tx_data0_export[19:0].
In a 20-lane variation, lane 0 is output on tx_data3_export[99:80],
lane 1 is output on tx_data3_export[79:60], and so on;
lane 5 is output on tx_data2_export[99:80],
lane 6 is output on tx_data2_export[79:60], and so on;
lane 10 is output on tx_data1_export[99:80];
lane 14 is output on tx_data1_export[19:0];
lane 15 is output on tx_data0_export[99:80], and
lane 19 is output on tx_data0_export[19:0].
Output