Altera Interlaken MegaCore Function - Manual (Page 82)

C–2 Appendix C: Closing Timing on 10- and 20-lane Designs
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
6. To set the parameters of the new Interlaken TX hierarchy LogicLock region, repeat
step 5 , with Width 58, Height 63, and Origin X7_Y1.
7. To create a LogicLock region for the clock-crossing FIFOs in the HSIO block,
perform the following steps:
a. In the LogicLock Regions window, in the Region Name column, double-click
<<new>> to create a new region.
b. In the new row, in the Region Name column, type a name for your new region
<FIFO_LLR>.
c. Right-click the <FIFO_LLR> row, and click LogicLock Regions Properties.
d. On the General tab, click Add. The Add Node dialog box appears.
e. For Node name, type *clock_crossing_fifo*.
f. Click OK.
g. In the LogicLock Regions Properties dialog box, click Apply.
h. On the Size & Origin tab, under Size, turn off Auto and set the Width to 3 and
the Height to 129.
i. Under Origin, turn off Floating and set Location string to X3_Y1.
j. Click Apply.
k. Click OK.
8. Repeat step 7 for a new region <IGX_IF> that includes the nodes that match
*launch* or *rx_capture* or *rx_dataout_to_fifo*, with Width 5, Height 129,
and Origin X1_Y1.