Sundance SMT370v2 - Manual (Page 40)

Version 2.0 Page 40 of 46 SMT370v2/v3 User Manual
The External Trigger signal is routed from connector J16 to the FPGA. Two clamping
diodes avoid too high amplitude signals to damage the FPGA.
Channel Enable allows using only one DAC channel. When one is disabled, its
corresponding FIFO is too.
Direct Transfer:
- When Direct To DAC mode selected (Bit22=’1’), samples follow the following
path: SHBB -> FPGA FIFO -> DAC. Data are first written into a FIFO at the
SHB clock rate and read out and routed to the DAC at the DAC sampling clock
rate. There is one FIFO per 16-bit SHB path. Each of them can contain up to
512 words (Version 2.3 of the FPGA firmware) or 2048 words of 16 bits
(Version 2.4 and above of the FPGA firmware).
- When Bit20=’0’, the Pattern Generator mode is enabled. The Pattern
Generator is a feature of the SMT370, which allows the user generating a
periodic signal without taking any external CPU resource. It consists in using
the on-board ZBTRAM memory. Here are the steps to follow:
o Load into register 0x7, a Pattern Size (Bit22=’0’, Bit20=’1’) and set Bits
24 and 25.
o Send Samples to be loaded into the memory on SHBB.
o Once sample transfer completed, send a ‘Start’ command.
Load Pattern Size: when Bit20 is set high, PatternSize is loaded into a register. It
also resets the Pattern Generator itself allowing then reloading a pattern of a different
size at any time.
Pattern Size: 20 bits are available to define the size of a pattern. One unit (bit)
defines a 32-bit value (two 16-bit synchronised DAC samples). A 20-bit size
corresponds to the maximum size of the on-board ZBTRAM.
Start/Stop: This to start or stop the pattern generator, i.e. the read back operation.
Make sure that a Start operation is not selected when loading data into memory for
pattern use. Data are written into the memory under the SHB clock and read out
under the DAC sampling clock.