Intel 41210 - Manual (Page 34)

34 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
PCI-X Layout Guidelines
Table 7. PCI/PCI-X Frequency/Mode Straps
Note: All signals sampled on the rising edge of PERST#.
8.3.1 PCI Pullup Resistors Not Required
PCI control signals on the 41210 Bridge do NOT require pullup resistors on the adapter card to
ensure that they contain stable values when no agent is actively driving the bus. These include:
A_ACK64#, A_AD[63:32], A_CBE#[7:4], A_DEVSEL#, A_FRAME#, A_INTA#, A_INTB#,
A_INTC#, A_INTD#, A_IRDY#, A_PERR#, A_PAR, A_GNT#[5:0], A_REQ#[5:0], A_LOCK#,
A_PAR64, A_REQ64#, A_SERR#, A_STOP#, A_TRDY#, B_ACK64#, B_AD[63:32],
Table 6. PCI-X Signals
Timing Critical Signals
A PCI Bus Segment:
A_ACK64#, A_AD[63:0], A_CBE_[7:0]#, A_DEVSEL#, A_FRAME#,
A_GNT_[5:0]#, A_IRDY#, A_LOCK#, A_PAR64, A_REQ64#, A_REQ_[5:0]#,
A_STOP#, A_TRDY#, A_CLKO[6:0], A_CLKI
B PCI Bus Segment:
B_ACK64#, B_AD[63:0], B_CBE_[7:0]#, B_DEVSEL#, B_FRAME#,
B_GNT_[5:0]#, B_IRDY#, B_LOCK#, B_PAR64, B_REQ64#, B_REQ_[5:0]#,
B_STOP#,B_TRDY#, B_CLKO[6:0], B_CLKI
Reset Signals
A PCI Bus Segment:
A_RST#, A_PME#
B PCI Bus Segment:
B_RST#, B_PME#
Non Timing Critical
Signals
A PCI Bus Segment:
A_133EN, A_IRQ[15:0]#, A_M66EN, A_PCIXCAP, A_PERR#, A_SERR#
B PCI Bus Segment:
B_133EN, B_IRQ[15:0]#, B_M66EN, B_PCIXCAP, B_PERR#, B_SERR#
A_PCIXCAP, B_PCIXCAP
A_M66EN,
B_M66EN
A_133EN,
B_133EN
(on board)
Bus
Mode/
Freq
0 0 X PCI 33
0 1 X PCI 66
PCI-X 66MHz cards connect this
signal to ground through a 10K
Ω
±5% resistor in parallel with a
0.01uF ±10% capacitor.
X X PCI-X 66
PCI-X 133 MHz cards connect
PCIXCAP to ground through a
0.01uF ±10% capacitor.
X 0 PCI-X 100
PCI-X 133 MHz cards connect
PCIXCAP to ground through a
0.01uF ±10% capacitor.
X 1 PCI-X 133