Intel 41210 - Manual (Page 41)

Intel® 41210 Serial to Parallel PCI Bridge Design Guide 41
PCI-X Layout Guidelines
8.6.3 PCI-X 66 MHz Embedded Topology
Figure 20 and Table 12 provide routing details for a topology with an embedded PCI-X 66 MHz
application.
Figure 20. PCI-X 66 MHz Embedded Routing Topology
Table 12. PCI-X 66 MHz Embedded Routing Recommendations
Parameter Routing Guideline for Lower AD Bus
Reference Plane Route over an unbroken ground plane
Board Impedance 60
Ω
+/- 15%
Stripline Trace Spacing 12 mils edge to edge
Microstrip Trace Spacing 18 mils, edge to edge
Break Out 5 mils on 5 mils. Maximum length of breakout region can be 500 mils
Group Spacing Spacing from other groups: 25 mils min, edge to edge
Trace Length 1 (TL1): From
41210 Bridge signal Ball to
first junction
1.0” - 5.0” max
Trace Length TL2 to TL4 -
between junctions
1.0” min - 2.5” max
Trace Length TL_EM1 to
TL_EM8 from junction
connector to the embedded
device
2.0” min - 3.0” max
Length Matching
Requirements: Clocks coming form the clock driver must be length matched to within 25 mils
and routed identical in layers.
Number of vias 4 vias max.
B2721 -01
EM1
EM2
TL1
TL_EM2
TL_EM1
EM3
EM4
TL2
TL_EM4
TL_EM3
EM5
EM6
TL3
TL_EM6
TL_EM5
EM7
EM8
TL4
TL_EM8
TL_EM7