NEC PD17062 - Manual (Page 230)

230
µ
PD17062
(2) PLL unlock FF delay control register (PLULSEN)
When the unlock FF disable mode is selected, the unlock FF remains set. So, note that if the PLL unlock
FF judge register checks the unlock FF in the unlock FF disable mode, it always appears to be unlocked
(PLLUL flag = 1).
Fig. 18-8 Configuration and Functions of the PLL Unlock FF Delay Control Register (PLULSEN)
P
L
U
L
S
E
N
3
Register
Flag symbol
b 3 b 2 b 1 b 0
P
L
U
L
S
E
N
1
P
L
U
L
S
E
N
0
32H R/W
Address Read/write
0
Upon reset
Power-on
Clock stop
CE
0 0
0
0 1
1 0
1 1
1.25-1.5 s or more
3.5-3.75 s or more
0.25-0.5 s or more
Unlock FF disabled (Always to be set)
0 0
0 0
Hold
Sets the delay time between the reference (f
r
) and division frequency (f
N
) signals,
which is necessary to set the unlock FF.
Fixed to 0.
PLL unlock FF
delay control
(PLULSEN)
Hold
P
L
U
L
S
E
N
2
µ
µ
µ