NEC PD17062 - Manual (Page 232)

232
µ
PD17062
PLLR
0000 0110 1100 1111
0 6 C F
PLRFMODE
0010
6.25 kHz
18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER
The following data is necessary to control the PLL frequency synthesizer.
(1) Reference frequency : f r
(2) Division value : N
The following paragraphs explain how to set the PLL data.
(1) Setting reference frequency f r
The reference frequency is specified according to the PLL reference mode select register.
(2) Calculating division value N
The division value N is calculated as follows:
N =
f UCO
P
×
f
r
where f UCO : Frequency input to the VCO pin
f
r
: Reference frequency
P : Prescaler frequency division ratio
(3) Example of setting the PLL data
The following example shows how to specify the data required to receive channel 02 of the West Europe
TV system, assuming that the prescaler used here is the
µ
PB595 and that the frequency division ratio P
is 8.
Receive frequency : 48.25 MHz
Reference frequency : 6.25 kHz
Intermediate frequency : 38.9 MHz
The division value N is calculated as follows:
N =
f UCO
=
48250 + 38900
= 1743 (decimal)
P
×
f
r
8
×
6.25
= 06CFH (hexadecimal)
The PLL data register (PLLR, at address 41H) and PLL reference mode select register (PLRFMOD, at address
13H) are set with data as shown below.