NEC PD78F9488 - Manual (Page 154)

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
User’s Manual U15331EJ4V1UD
154
7.4.4 PWM output mode operation (timer 50)
In the PWM output mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when
CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio (free-running).
To operate timer 50 in the PWM output mode, settings must be made in the following sequence.
<1> Disable operation of TM50 (TCE50 = 0).
<2> Disable timer output of TO50 (TOE50 = 0).
<3> Set a count value to CR50.
<4> Set the operation mode of timer 50 to the PWM output mode (see Figure 7-6).
<5> Set the count clock for timer 50.
<6> Set P30 to the output mode (PM30 = 0) and the P30 output latch to 0 and enable timer output of TO50
(TOE50 = 1).
<7> Enable the operation of TM50 (TCE50 = 1).
The operation in the PWM output mode is as follows.
<1> When the count value of TM50 matches the value set in CR50, an interrupt request signal (INTTM50) is
generated and a low level is output by the TO50. The TM50 continues counting without being cleared.
<2> TO50 outputs a high level when the TM50 overflows.
A pulse of any duty is output by repeating the above procedure. Figures 7-25 to 7-28 show the operation timing in
the PWM output mode.
Figure 7-25. Operation Timing in PWM Output Mode (When Rising Edge Is Selected)
Count clock
CR50
TCE50
INTTM50
TO50
N
TM50 N 00H 00H 00H 01H FFH N FFH N
Overflow Overflow Overflow
Count start
Caution When the rising edge is selected, do not set CR50 to 00H. If CR50 is set to 00H, PWM output
may not be performed normally.
Remark N = 00H to FFH