NEC PD78F9488 - Manual (Page 311)

CHAPTER 17 STANDBY FUNCTION
User’s Manual U15331EJ4V1UD
311
(c) Release by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.
Figure 17-3. Releasing HALT Mode by RESET Input
HALT
instruction
RESET
signal
Wait
(2 15 /f
X
: 6.55 ms)
Reset
period HALT mode
Operation
mode
Oscillation
stabilization
wait status
Clock
Operation
mode
Oscillation
stops Oscillation Oscillation
Remark f
X
: Main system clock oscillation frequency
Table 17-2. Operation After Releasing HALT Mode
Releasing Source MKxx IE Operation
0 0 Executes next address instruction
0 1 Executes interrupt servicing
Maskable interrupt request
1 x Retains HALT mode
Non-maskable interrupt request − x Executes interrupt servicing
RESET input - − - − Reset processing
x: don’t care
Caution Some constraints apply when the flash version ( µPD78F9488 and 78F9489) is used in the HALT
mode with the subclock multiplied by 4 as the CPU clock. For details, refer to 19.2 Cautions on
µPD78F9488 and 78F9489.