Compatibility testing environment, Performance and resource utilization, V-series recommended speed grades – Altera V-Series Avalon-MM DMA User Manual
Page 10
Compatibility Testing Environment
Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera
internally tests every release with motherboards and PCI Express switches from a variety of manufac‐
turers. All PCI-SIG compliance tests are run with each IP core release.
Performance and Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device
resources.
The V-Series variants include a soft logic bridge that functions as a front end to the hardened protocol
stack. The following table shows the typical expected device resource utilization for selected configura‐
tions using the current version of the Quartus II software targeting a V-Series device. With the exception
of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.
Table 1-5: Performance and Resource Utilization V-Series Avalon-MM DMA for PCI Express
Interface Width
ALMs
M20K Memory Blocks
Logic Registers
128
1100
14
1650
256
1750
19
2600
Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required
depends upon the configuration.
Related Information
V-Series Recommended Speed Grades
Altera recommends setting the Quartus II Analysis & Synthesis Settings Optimization Technique to
Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing
synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus II Help. For more informa‐
tion about how to effect the Optimization Technique settings, refer to Area and Timing Optimization in
volume 2 of the Quartus II Handbook. .
UG-01154
2014.12.18
Compatibility Testing Environment
1-9
Datasheet
Altera Corporation
- MAX 10 JTAG
- MAX 10 Power
- Unique Chip ID
- Remote Update IP Core
- Device-Specific Power Delivery Network
- Device-Specific Power Delivery Network
- Hybrid Memory Cube Controller
- ALTDQ_DQS IP
- MAX 10 Embedded Memory
- MAX 10 Embedded Multipliers
- MAX 10 Clocking and PLL
- MAX 10 FPGA
- MAX 10 FPGA
- USB-Blaster II
- GPIO
- LVDS SERDES
- User Flash Memory
- ALTDQ_DQS2
- Avalon Tri-State Conduit Components
- Cyclone V Avalon-MM
- Cyclone V Avalon-MM
- Cyclone III FPGA Starter Kit
- Cyclone V Avalon-ST
- Cyclone V Avalon-ST
- Stratix V Avalon-ST
- Stratix V Avalon-ST
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP
- Arria 10 Avalon-ST
- Avalon Verification IP Suite
- Avalon Verification IP Suite
- FFT MegaCore Function
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP
- Floating-Point
- Integer Arithmetic IP
- Embedded Peripherals IP
- JESD204B IP
- Low Latency Ethernet 10G MAC
- LVDS SERDES Transmitter / Receiver
- Nios II Embedded Evaluation Kit Cyclone III Edition
- Nios II Embedded Evaluation Kit Cyclone III Edition
- IP Compiler for PCI Express
- Parallel Flash Loader IP
- Nios II C2H Compiler
- RAM-Based Shift Register
- RAM Initializer
- Phase-Locked Loop Reconfiguration IP Core
- DCFIFO
- SDI II MegaCore
- SerialLite II IP Core
- Serial Digital Interface (SDI) MegaCore Function
- 100G Development Kit, Stratix V GX Edition
- 100G Development Kit, Stratix V GX Edition
- 100G Interlaken MegaCore Function
- Arria V GZ Avalon-MM
- Arria V GZ Avalon-MM
- 10-Gbps Ethernet MAC MegaCore Function
- Triple Speed Ethernet MegaCore Function
- 8B10B Encoder/Decoder MegaCore Function
- 50G Interlaken MegaCore Function
- Advanced SEU Detection IP Core
- Active Serial Memory Interface
- I/O Phase-Locked Loop (Altera IOPLL) IP Core
- OCT
- Embedded Systems Development Kit, Cyclone III Edition
- Phase-Locked Loop
- 100-Gbps Ethernet MAC and PHY MegaCore Function
- SDK for OpenCL Cyclone V SoC
- PHYLite
- RTE for OpenCL
- ALTPLL (Phase-Locked Loop) IP Core
- Arria 10 Avalon-MM DMA
- Arria GX
- Cyclone IV GX FPGA
- Arria II GX FPGA
- Cyclone IV GX FPGA
- Arria 10 Avalon-MM
- SoC Embedded Design Suite
- Arria V GX
- Arria V GX FPGA
- Arria V GX FPGA
- Arria V SoC
- Arria V Hard IP for PCI Express
- ASI MegaCore Function
- Transceiver PHY IP Core
- ByteBlaster II
- Audio Video Development Kit, Stratix IV GX Edition
- ByteBlasterMV
- Clock Control Block IP Core
- CIC MegaCore Function
- CRC Compiler
- CPRI v6.0 MegaCore Function
- Cyclone II FPGA Starter
- Cyclone II PowerPlay Early Power Estimator
- Cyclone III LS FPGA
- CPRI IP Core
- Cyclone V E FPGA
- Cyclone V GT FPGA
- Cyclone V GX FPGA
- Cyclone V SoC
- DDR2 SDRAM Controller
- DDR Timing Wizard
- Designing With Low-Level Primitives
- Double Data Rate I/O
- DQS (ALTDQS)
- DSP Development Kit, Cyclone II Edition Getting Started
- DSP Development Kit, Stratix & Stratix Professional Edition Getting Started
- Dynamic Calibrated On-Chip Termination
- Stratix V GX FPGA
- Stratix V GX FPGA
- DSP Development Kit, Stratix V Edition
- Early SSN Estimator
- DisplayPort MegaCore Function
- EthernetBlaster II
- FIR Compiler II MegaCore Function
- First-In-First-Out Partitioner
- FIR Compiler
- External Memory PHY Interface
- HardCopy II Clock Uncertainty Calculator
- I/O Buffer (ALTIOBUF) IP Core
- HyperTransport MegaCore Function
- Interlaken MegaCore Function
- High-Speed Development Kit, Stratix GX Edition
- Internal Memory (RAM and ROM) IP Core
- MasterBlaster Serial/USB
- MAX II
- MAX V CPLD
- Low Latency 100-Gbps Ethernet MAC and PHY MegaCore Function
- JNEye
- Mentor Verification IP Altera Edition AMBA AXI4-Lite
- NCO MegaCore Function
- Mentor Verification IP Altera Edition AMBA AXI4-Stream
- Nios II
- Nios II
- Nios II
- Nios II Custom
- Mentor Verification IP Altera Edition AMBA AXI3/4TM
- Partial Reconfiguration IP Core
- PCI Development Kit, Cyclone II Edition Getting Started
- PCI Express Development Kit, Stratix II GX Edition Getting Started
- POS-PHY Level 2 and 3 Compiler
- Power Delivery Network
- POS-PHY Level 4 IP Core
- PowerPlay Early Power Estimator for Altera CPLDs
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PCI Compiler
- QDRII SRAM Controller MegaCore Function
- Reed-Solomon Compiler
- Reed-Solomon II MegaCore Function
- RLDRAM II Controller MegaCore Function
- SDI Audio IP Cores
- Shift Register IP Core
- RapidIO II MegaCore Function
- RapidIO MegaCore Function
- SerialLite III Streaming MegaCore Function
- Transceiver Signal Integrity
- Transceiver Signal Integrity
- Stratix II GX Embedded Gigabit Ethernet MAC/PHY
- Stratix III
- Stratix IV E FPGA
- Stratix IV GX FPGA
- Stratix IV GX FPGA
- Stratix IV GT 100G
- Stratix V Advanced Systems
- Temperature Sensor
- Transceiver SI
- Transceiver Signal Integrity
- Transceiver Signal Integrity
- Stratix GX Transceiver
- USB Blaster
- Stratix V Avalon-ST
- Virtual JTAG IP Core
- Viterbi Compiler
- Cyclone V GT FPGA Development Board
- 100G Development Kit, Stratix IV GT Edition
- Stratix V GX FPGA Development Board
- Arria II GX FPGA Development Board
- Arria II GX FPGA Development Board, 6G Edition
- Cyclone V E FPGA Development Board
- Cyclone IV GX Transceiver Starter Board
- Cyclone V SoC Development Board
- Video and Image Processing Suite
- MAX V CPLD Development Board
- SDI HSMC
- SDC and TimeQuest API
- Stratix IV GX FPGA Development Board
- Stratix IV GX FPGA Development Board
- Stratix IV E FPGA Development Board
- Transceiver Signal Integrity Development Kit, Stratix IV GT Edition
- Transceiver Signal Integrity Development Kit, Stratix V GX Edition
- Arria GX Development Board
- Arria V GT FPGA Development Board
- Arria V GX FPGA Development Board
- Arria V GX Starter Board
- Quartus II Scripting
- Arria V SoC Development Board
- Cyclone II EP2C35 PCI Development Board
- Cyclone II DSP Development Board
- Cyclone II FPGA Starter Development Board
- Cyclone III FPGA Starter Board
- Cyclone III Development Board
- Cyclone III LS FPGA Development Board
- Cyclone IV GX FPGA Development Board
- Cyclone V GX FPGA Development Board
- Multiaxis Motor Control Board
- Data Conversion HSMC
- LCD Multimedia HSMC
- Nios Development Board Cyclone II Edition
- Nios Development Board
- Nios Development Board
- Nios Development Board
- Nios Development Board
- Quartus II
- Nios Development Board Stratix II Edition
- Santa SD Card HSMC
- Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board
- Stratix II EP2S180 DSP Development Board
- SerialLite II Protocol
- Stratix II GX PCI Express Development Board
- Stratix III Development Board
- Transceiver Signal Integrity Development Kit, Stratix IV GX Edition
- Stratix V Advanced Systems Development Board
- Transceiver Signal Integrity Development Kit, Stratix V GT Edition
- Quartus II Settings File