Altera V-Series Avalon-MM DMA - Manual (Page 9)

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide
• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide
Example Designs
The following Qsys example designs are available for the V-Series Avalon-MM DMA for PCI Express IP
Core. You can download them from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/
example_design/<dev> directory:
• pcie_de_ep_dma_g3x8_integrated.qsys—Arria V GZ and Stratix V
• pcie_de_ep_dma_g3x8. qsys—Arria V GZ and Stratix V
• pcie_de_ep_dma_g1x8_av_integrated. qsys—Arria V
• pcie_de_ep_g2x4_cv. qsys—Cyclone V
Related Information
Getting Started with the Avalon-MM DMA on page 2-1
Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
IP Core Verification
To ensure compliance with the PCI Express specification, Altera performs extensive verification. The
simulation environment uses multiple testbenches that consist of industry-standard bus functional
models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the
simulation environment:
• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration
Space, and all types and sizes of TLPs
• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and
check for the proper responses
• PCI-SIG ® Compliance Checklist tests that specifically test the items in the checklist
• Random tests that test a wide range of traffic patterns
Altera provides the following two example designs that you can leverage to test your PCBs and complete
compliance base board testing (CBB testing) at PCI-SIG.
Related Information
• PCI SIG Gen3 x8 Merged Design - Stratix V
• PCI SIG Gen2 x8 Merged Design - Stratix V
1-8 Example Designs
UG-01154
2014.12.18
Altera Corporation Datasheet
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