Physical layer interface signals, Transceiver reconfiguration – Altera V-Series Avalon-MM DMA User Manual
Page 52
Signal
Direction
Description
MSIControl_o[15:0]
Output
Provides system software control of the MSI messages as defined
in Section 6.8.1.3 Message Control for MSI in the PCI Local Bus
Specification, Rev. 3.0. The following fields are defined:
•
MSIControl_o[15:9]
: Reserved
•
MSIControl_o[8]
: Per-Vector Masking Capable
•
MSIControl_o[7]
: 64-Bit Address Capable
•
MSIControl_o[6:4]
: Multiple Message Enable
•
MSIControl_o[3:1]
: MSI Message Capable
•
MSIControl_o[0]
: MSI Enable
Physical Layer Interface Signals
Altera provides an integrated solution with the Transaction, Data Link and Physical Layers. The IP
Parameter Editor generates a SERDES variation file,
<variation>_serdes.v
or .vhd , in addition to the Hard
IP variation file,
<variation>.v
or
.vhd
. The SERDES entity is included in the library files for PCI Express.
Transceiver Reconfiguration
Dynamic reconfiguration compensates for variations due to process, voltage and temperature (PVT).
Among the analog settings that you can reconfigure are V
OD
, pre-emphasis, and equalization.
You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure analog
settings. For more information about instantiating the Altera Transceiver Reconfiguration Controller IP
core refer to Hard IP Reconfiguration .
Table 4-20: Transceiver Control Signals
In this table, <n> is the number of interfaces required.
Signal Name
Direction
Description
reconfig_from_
xcvr[(<n>46)-1:0]
Output
Reconfiguration signals to the Transceiver Reconfiguration
Controller.
reconfig_to_xcvr[(<n>
70)-1:0]
Input
Reconfiguration signals from the Transceiver Reconfiguration
Controller.
reconfig_clk_locked
Output
When asserted, indicates that the PLL that provides the fixed
clock required for transceiver initialization is locked. The
Application Layer should be held in reset until
reconfig_clk_
locked
is asserted.
The following table shows the number of logical reconfiguration and physical interfaces required for
various configurations. The Quartus II Fitter merges logical interfaces to minimize the number of physical
interfaces configured in the hardware. Typically, one logical interface is required for each channel and one
UG-01154
2014.12.18
Physical Layer Interface Signals
4-21
Interfaces and Signal Descriptions
Altera Corporation
- MAX 10 JTAG
- MAX 10 Power
- Unique Chip ID
- Remote Update IP Core
- Device-Specific Power Delivery Network
- Device-Specific Power Delivery Network
- Hybrid Memory Cube Controller
- ALTDQ_DQS IP
- MAX 10 Embedded Memory
- MAX 10 Embedded Multipliers
- MAX 10 Clocking and PLL
- MAX 10 FPGA
- MAX 10 FPGA
- USB-Blaster II
- GPIO
- LVDS SERDES
- User Flash Memory
- ALTDQ_DQS2
- Avalon Tri-State Conduit Components
- Cyclone V Avalon-MM
- Cyclone V Avalon-MM
- Cyclone III FPGA Starter Kit
- Cyclone V Avalon-ST
- Cyclone V Avalon-ST
- Stratix V Avalon-ST
- Stratix V Avalon-ST
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP
- Arria 10 Avalon-ST
- Avalon Verification IP Suite
- Avalon Verification IP Suite
- FFT MegaCore Function
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP
- Floating-Point
- Integer Arithmetic IP
- Embedded Peripherals IP
- JESD204B IP
- Low Latency Ethernet 10G MAC
- LVDS SERDES Transmitter / Receiver
- Nios II Embedded Evaluation Kit Cyclone III Edition
- Nios II Embedded Evaluation Kit Cyclone III Edition
- IP Compiler for PCI Express
- Parallel Flash Loader IP
- Nios II C2H Compiler
- RAM-Based Shift Register
- RAM Initializer
- Phase-Locked Loop Reconfiguration IP Core
- DCFIFO
- SDI II MegaCore
- SerialLite II IP Core
- Serial Digital Interface (SDI) MegaCore Function
- 100G Development Kit, Stratix V GX Edition
- 100G Development Kit, Stratix V GX Edition
- 100G Interlaken MegaCore Function
- Arria V GZ Avalon-MM
- Arria V GZ Avalon-MM
- 10-Gbps Ethernet MAC MegaCore Function
- Triple Speed Ethernet MegaCore Function
- 8B10B Encoder/Decoder MegaCore Function
- 50G Interlaken MegaCore Function
- Advanced SEU Detection IP Core
- Active Serial Memory Interface
- I/O Phase-Locked Loop (Altera IOPLL) IP Core
- OCT
- Embedded Systems Development Kit, Cyclone III Edition
- Phase-Locked Loop
- 100-Gbps Ethernet MAC and PHY MegaCore Function
- SDK for OpenCL Cyclone V SoC
- PHYLite
- RTE for OpenCL
- ALTPLL (Phase-Locked Loop) IP Core
- Arria 10 Avalon-MM DMA
- Arria GX
- Cyclone IV GX FPGA
- Arria II GX FPGA
- Cyclone IV GX FPGA
- Arria 10 Avalon-MM
- SoC Embedded Design Suite
- Arria V GX
- Arria V GX FPGA
- Arria V GX FPGA
- Arria V SoC
- Arria V Hard IP for PCI Express
- ASI MegaCore Function
- Transceiver PHY IP Core
- ByteBlaster II
- Audio Video Development Kit, Stratix IV GX Edition
- ByteBlasterMV
- Clock Control Block IP Core
- CIC MegaCore Function
- CRC Compiler
- CPRI v6.0 MegaCore Function
- Cyclone II FPGA Starter
- Cyclone II PowerPlay Early Power Estimator
- Cyclone III LS FPGA
- CPRI IP Core
- Cyclone V E FPGA
- Cyclone V GT FPGA
- Cyclone V GX FPGA
- Cyclone V SoC
- DDR2 SDRAM Controller
- DDR Timing Wizard
- Designing With Low-Level Primitives
- Double Data Rate I/O
- DQS (ALTDQS)
- DSP Development Kit, Cyclone II Edition Getting Started
- DSP Development Kit, Stratix & Stratix Professional Edition Getting Started
- Dynamic Calibrated On-Chip Termination
- Stratix V GX FPGA
- Stratix V GX FPGA
- DSP Development Kit, Stratix V Edition
- Early SSN Estimator
- DisplayPort MegaCore Function
- EthernetBlaster II
- FIR Compiler II MegaCore Function
- First-In-First-Out Partitioner
- FIR Compiler
- External Memory PHY Interface
- HardCopy II Clock Uncertainty Calculator
- I/O Buffer (ALTIOBUF) IP Core
- HyperTransport MegaCore Function
- Interlaken MegaCore Function
- High-Speed Development Kit, Stratix GX Edition
- Internal Memory (RAM and ROM) IP Core
- MasterBlaster Serial/USB
- MAX II
- MAX V CPLD
- Low Latency 100-Gbps Ethernet MAC and PHY MegaCore Function
- JNEye
- Mentor Verification IP Altera Edition AMBA AXI4-Lite
- NCO MegaCore Function
- Mentor Verification IP Altera Edition AMBA AXI4-Stream
- Nios II
- Nios II
- Nios II
- Nios II Custom
- Mentor Verification IP Altera Edition AMBA AXI3/4TM
- Partial Reconfiguration IP Core
- PCI Development Kit, Cyclone II Edition Getting Started
- PCI Express Development Kit, Stratix II GX Edition Getting Started
- POS-PHY Level 2 and 3 Compiler
- Power Delivery Network
- POS-PHY Level 4 IP Core
- PowerPlay Early Power Estimator for Altera CPLDs
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PowerPlay Early Power Estimator
- PCI Compiler
- QDRII SRAM Controller MegaCore Function
- Reed-Solomon Compiler
- Reed-Solomon II MegaCore Function
- RLDRAM II Controller MegaCore Function
- SDI Audio IP Cores
- Shift Register IP Core
- RapidIO II MegaCore Function
- RapidIO MegaCore Function
- SerialLite III Streaming MegaCore Function
- Transceiver Signal Integrity
- Transceiver Signal Integrity
- Stratix II GX Embedded Gigabit Ethernet MAC/PHY
- Stratix III
- Stratix IV E FPGA
- Stratix IV GX FPGA
- Stratix IV GX FPGA
- Stratix IV GT 100G
- Stratix V Advanced Systems
- Temperature Sensor
- Transceiver SI
- Transceiver Signal Integrity
- Transceiver Signal Integrity
- Stratix GX Transceiver
- USB Blaster
- Stratix V Avalon-ST
- Virtual JTAG IP Core
- Viterbi Compiler
- Cyclone V GT FPGA Development Board
- 100G Development Kit, Stratix IV GT Edition
- Stratix V GX FPGA Development Board
- Arria II GX FPGA Development Board
- Arria II GX FPGA Development Board, 6G Edition
- Cyclone V E FPGA Development Board
- Cyclone IV GX Transceiver Starter Board
- Cyclone V SoC Development Board
- Video and Image Processing Suite
- MAX V CPLD Development Board
- SDI HSMC
- SDC and TimeQuest API
- Stratix IV GX FPGA Development Board
- Stratix IV GX FPGA Development Board
- Stratix IV E FPGA Development Board
- Transceiver Signal Integrity Development Kit, Stratix IV GT Edition
- Transceiver Signal Integrity Development Kit, Stratix V GX Edition
- Arria GX Development Board
- Arria V GT FPGA Development Board
- Arria V GX FPGA Development Board
- Arria V GX Starter Board
- Quartus II Scripting
- Arria V SoC Development Board
- Cyclone II EP2C35 PCI Development Board
- Cyclone II DSP Development Board
- Cyclone II FPGA Starter Development Board
- Cyclone III FPGA Starter Board
- Cyclone III Development Board
- Cyclone III LS FPGA Development Board
- Cyclone IV GX FPGA Development Board
- Cyclone V GX FPGA Development Board
- Multiaxis Motor Control Board
- Data Conversion HSMC
- LCD Multimedia HSMC
- Nios Development Board Cyclone II Edition
- Nios Development Board
- Nios Development Board
- Nios Development Board
- Nios Development Board
- Quartus II
- Nios Development Board Stratix II Edition
- Santa SD Card HSMC
- Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board
- Stratix II EP2S180 DSP Development Board
- SerialLite II Protocol
- Stratix II GX PCI Express Development Board
- Stratix III Development Board
- Transceiver Signal Integrity Development Kit, Stratix IV GX Edition
- Stratix V Advanced Systems Development Board
- Transceiver Signal Integrity Development Kit, Stratix V GT Edition
- Quartus II Settings File