Zilog Z80180 - Manual (Page 297)

Z8018x
Family MPU User Manual
281
UM005003-0703
Operating Modes Summary
REQUEST ACCEPTANCES IN EACH OPERATING MODE
Table 53. Request Acceptances in Each Operating Mode
Current
Status
Request
Normal
Operation
(CPU mode
and IOSTOP
Mode)
WAIT State
Refresh
Cycle
Interrupt
Acknowledge
Cycle
DMA Cycle
BUS
RELEASE
Mode
SLEEP
Mode
SYSTEM
STOP
Mode
WAIT Acceptable Acceptable Not
acceptable Acceptable Acceptable Not
acceptable Not
acceptable Not
acceptable
Refresh Request
Request of Refresh
by the on-chip
Refresh Controller Refresh cycle
begins at the
end of Machine
Cycle (MC) Not
acceptable Not
acceptable Refresh cycle
begins at the
end MC Refresh cycle
begins at the
end of MC Not
acceptable Not
acceptable Not
acceptable
DREQ0
DREQ1 DMA cycle
begins at the
end of MC DMA cycle
begins at the
end of MC Acceptable
Refresh cycle
precedes.
DMA cycle
begins at the
end of one
MC Acceptable
DMA cycle
begins at the
end of MC. Acceptable
Refer to
“DMA
Controller”
for details. Acceptable
*After BUS
RELEASE
cycle, DMA
cycle begins
at the end of
one MC Not
acceptable Not
acceptable
BUSREQ Bus is released
at the end of
MC Not
acceptable Not
acceptable Bus is released
at the end of
MC Bus is
released at the
end of MC Continue
BUS
RELEASE
mode Acceptable Acceptable
Interrupt INT0,
INT1,
1NT2
Accepted after
executing the
current
instruction. Accepted
after
executing the
current
instruction Not
acceptable Not
acceptable Not
acceptable Not
acceptable Acceptable
Return from
SLEEP
mode to
normal
operation. Acceptable
Return from
SYSTEM
STOP mode
to normal
operation