Zilog Z80180 - Manual (Page 71)

Z8018x
Family MPU User Manual
56
UM005003-0703
Figure 24. Physical Address Transition
MMU Block Diagram
The MMU block diagram is depicted in Figure 25. The MMU translates
internal 16-bit logical addresses to external 20-bit physical addresses.
Figure 25. MMU Block Diagram
Logical Address Space
Physical Address Space
Common Area 1
Bank Area
Common Area 0
Common Base
Bank Base
FFFFH
0000H
FFFFFH
00000H
0
+
+
+
x y z
z
y
x
MMU Common/Bank Area
Register; CBAR (8) Memory
Management
8
PA12—PA19
LA12—LA15
4
MMU Common Base
Register; CBR (8)
MMU Bank Base
Register; BBR (8)
LA: Logical Address
PA: Physical Address
Internal Address/Data Bus
Unit