Zilog Z80180 - Manual (Page 314)

Z8018x
Family MPU User Manual
298
UM005003-0703
Timer Data Register
Channel 1L:
Timer Data Register
Channel 1H:
Timer Reload Register
Channel 1L
Timer Reload Register
Channel 1H:
Free Running Counter:
DMA Source Address
Register Channel 0L:
DMA Source Address
Register Channel 0H:
DMA Source Address
Register Channel 0B:
DMA Destination Address
Register Channel 0L:
DMA Destination Address
Register Channel 0H:
DMA Destination Address
Register Channel 0B:
DMA Byte Count Register
Channel 0L:
DMA Byte Count Register
Channel 0H:
DMA Memory Address
Register
Channel 1L:
DMA Memory Address
Register
Channel 1H: TMDR1L
TMDR1H
RLDR1L
RLDR1H
FRC
SAR0L
SAR0H
SAR0B
DAR0L
DAR0H
DAR0B
BCROL
BCROH
MAR1L
MAR1H
1 4
1 5
1 6
1 7
1 8
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
Table 57. Internal I/O Registers (Continued)
Register Mnemonics Address Remarks
Bits 0-2 (3) are used for SAR0B
A 19 *, A 18 , A 17 , A 16
X
X
X
X X
X
X
X 0
0
1
1 0
1
0
1
DMA Transfer Request
DREQ 0 (external)
RDR0 (ASCI0)
RDR1 (ASCI1)
Not used
Bits 0-2 (3) are used for DAR0B
A
19
*, A
18
, A
17
, A
16
X
X
X
X X
X
X
X 0
0
1
1 0
1
0
1
DMA Transfer Request
DREQ 0 (external)
TDR0 (ASCI0)
TDR1 (ASCI1)
Not used
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.
Read only