Altera CPRI v6.0 MegaCore Function - Manual (Page 102)

Table 5-16: CPRI v6.0 IP Core TX_CTRL Register at Offset 0x34
Frequency differences between the control and status interface clock
cpu_clk
and the main CPRI v6.0 IP core
clock
cpri_clkout
might cause non-zero read latency and more than one clock cycle of write latency when
accessing this register.
Bits Field Name Type Value on
Reset
Description
31:0
tx_ctrl_
data
RW 32'b0 CPRI control word 32-bit section to be transmitted in CPRI
hyperframe position Z.x, where x is the index in the
tx_ctrl_x
field of the
CTRL_INDEX
register. The
tx_ctrl_seq
field of the
CTRL_INDEX
register indicates whether this is the first, second,
third, fourth, or fifth such 32-bit section.
RX_CTRL Register
Table 5-17: CPRI v6.0 IP Core RX_CTRL Register at Offset 0x38
Frequency differences between the control and status interface clock
cpu_clk
and the main CPRI v6.0 IP core
clock
cpri_clkout
might cause non-zero read latency and more than one clock cycle of write latency when
accessing this register.
Bits Field Name Type Value on
Reset
Description
31:0
rx_ctrl_
data
RO 32'b0 Most recent received CPRI control word 32-bit section from
CPRI hyperframe position Z.x, where x is the index in the
rx_
ctrl_x
field of the
CTRL_INDEX
register. The
rx_ctrl_seq
field
of the
CTRL_INDEX
register indicates whether this is the first,
second, third, fourth, or fifth such 32-bit section.
RX_ERR Register
Table 5-18: CPRI v6.0 IP Core RX_ERR Register at Offset 0x3C
Bits Field Name Type Value on
Reset
Description
31:16 Reserved UR0 16'b0
15:8
sh_err
RC 8'b0 Number of 64B/66B sync header violations detected in the
transceiver. Enables CPRI link debugging. This register turns
over to the value of 0 when it increments from the value of 255.
UG-01156
2015.02.16
RX_CTRL Register 5-13
CPRI v6.0 IP Core Registers Altera Corporation
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