Start_up_timer register, Start_up_timer register -10 – Altera CPRI v6.0 MegaCore Function User Manual
Page 99

Bits
Field Name
Type
Value on
Reset
Description
10:8
state_
startup_
seq
RO
3'b0
Indicates the current state of the start-up sequence. This field
has the following valid values:
• 3'b000: State A: Standby
• 3'b001: State B: L1 Synchronization
• 3'b011: State C: Protocol Setup
• 3'b010: State D: Control and Management Setup
• 3'b110: State E: Interface and VSS Negotiation
• 3'b111: State F: Operation
• 3'b101: State G: Passive Link
7:4
Reserved
UR0
4'b0
3
nego_vss_
complete
RW
1'b0
Indicates the Vendor Specific negotiation is complete. You
must set this bit to move the start-up sequence state machine
from state E to state F. If you turn on Enable start-up sequence
state machine, the
nego_vss_complete
input signal writes
directly to this register bit.
2
nego_cm_
complete
RW
1'b0
Indicates the Control and Management negotiation is complete
and the start-up sequence state machine can move from state D
to state E. If the
slow_cm_rate_auto
field or the
fast_cm_ptr_
auto
field, or both, in the
CM_CONFIG
register has the value of 1,
the IP core updates this bit if the user does not update it.
If you turn on Enable start-up sequence state machine, the
nego_cm_complete
input signal writes directly to this register
bit.
1
nego_
protocol_
complete
RW
1'b0
Indicates the protocol version negotiation is complete and the
start-up sequence state machine can move from state C to state
D. If the
prot_ver_auto
field of the
PROT_VER
register has the
value of 1, the IP core updates this bit if the user does not
update it.
If you turn on Enable start-up sequence state machine, the
nego_protocol_complete
input signal writes directly to this
register bit.
0
nego_
bitrate_
complete
RW
1'b0
Indicates the CPRI line bit rate negotiation is complete.
If you turn on Enable start-up sequence state machine, the
nego_bitrate_complete
input signal writes directly to this
register bit.
START_UP_TIMER Register
5-10
START_UP_TIMER Register
UG-01156
2015.02.16
Altera Corporation
CPRI v6.0 IP Core Registers