Altera CPRI v6.0 MegaCore Function - Manual (Page 2)

Contents
About the CPRI v6.0 IP Core.............................................................................. 1-1
CPRI v6.0 IP Core Supported Features.....................................................................................................1-2
CPRI v6.0 IP Core Device Family and Speed Grade Support................................................................1-3
Device Family Support....................................................................................................................1-3
CPRI v6.0 IP Core Performance: Device Speed Grade Support................................................1-4
IP Core Verification.....................................................................................................................................1-4
Resource Utilization for CPRI v6.0 IP Cores........................................................................................... 1-4
Release Information.....................................................................................................................................1-6
Installation and Licensing Features...........................................................................................................1-6
OpenCore Plus Evaluation............................................................................................................. 1-6
OpenCore Plus Time-Out Behavior..............................................................................................1-7
Getting Started with the CPRI v6.0 IP Core.......................................................2-1
Installation and Licensing...........................................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-2
Files Generated for Altera IP Cores...........................................................................................................2-3
CPRI v6.0 IP Core Parameters...................................................................................................................2-7
Integrating Your IP Core in Your Design: Required External Blocks................................................2-11
Adding the Clean-Up PLL............................................................................................................2-12
Adding the External TX PLL........................................................................................................2-13
Adding the External Reset Controller.........................................................................................2-14
Adding the Transceiver Reconfiguration Controller................................................................2-15
Simulating Altera IP Cores.......................................................................................................................2-16
Understanding the Testbench..................................................................................................................2-17
Running the Testbench.............................................................................................................................2-17
Functional Description....................................................................................... 3-1
Interfaces Overview..................................................................................................................................... 3-1
CPRI v6.0 IP Core Clocking Structure......................................................................................................3-3
CPRI v6.0 IP Core Reset Requirements....................................................................................................3-5
Start-Up Sequence Following Reset.......................................................................................................... 3-6
AUX Interface...............................................................................................................................................3-9
AUX Interface Signals................................................................................................................... 3-10
AUX Interface Synchronization.................................................................................................. 3-17
Auxiliary Latency Cycles...............................................................................................................3-17
Direct Interface CPRI Frame Data Format................................................................................ 3-18
Direct IQ Interface.....................................................................................................................................3-21
Direct Vendor Specific Access Interface.................................................................................................3-23
Real-Time Vendor Specific Interface......................................................................................................3-25
Direct HDLC Serial Interface...................................................................................................................3-27
Direct L1 Control and Status Interface...................................................................................................3-29
TOC-2 CPRI v6.0 MegaCore Function User Guide
Altera Corporation