Motorola DSP96002 - Manual (Page 117)

MOTOROLA DSP96002 USER’S MANUAL 7 - 31
The HI interrupt requests to the external host processor use the Host Request
—
H
–
R pin.
—
H
–
R is normally
connected to a host processor interrupt input. The host processor acknowledges HI interrupts by executing
an interrupt service routine. The MC680x0 processor family will assert the
—
T
–
S pin when both
—
H
–
R and
—
H
–
A are asserted to read the exception vector number from the IVR register of the HI. In a multi-
DSP96002 system, the HREQ bit in the Interrupt Status Register (ICS) may be tested to determine which
DSP96002 HI is the interrupting device and the RXDF, TXDE and TRDY bits may then be tested to deter-
mine the interrupt source. The host processor interrupt service routine must read or write the appropriate
HI register to clear the interrupt and deassert
—
H
–
R.
7.4.17 Host Processor Programmer Considerations
7.4.17.1 Reading RX
When reading the Receive register RX, the host processor programmer should use interrupts or poll the
RXDF flag which indicates that data is available. This guarantees that the data in the RX register will be
stable.
7.4.17.2 Writing TX
The host processor programmer should not write to the Transmit register TX unless the TXDE bit is set,
indicating that the TX register is empty. This guarantees that the HI will transfer stable data to the HRX reg-
ister on the DSP96002 side.
7.4.17.3 Synchronization of Status Bits from DSP96002 to Host Processor
HC, HMRC, HREQ, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from the DSP96002
side of the HI and read by the host processor. The host processor is able to read these status bits without
regard to the clock rate used by the DSP96002, but there is a chance that the state of the bit could be chang-
ing during the read operation. This is generally not a system problem, since, if the bit is changing, the read
will indicate that another poll should be taken and the bit will be read correctly in the next pass of the polling
routine.
The only potential system problem with the uncertainty of reading any status bits by the Host is when HF3
and HF2 are being used as an encoded pair. For example, if the DSP96002 changes HF3 and HF2 from
"00" to "11" there is a very small probability that the host processor could read the bits during the transition
and receive "01" or "10" instead of "11". If the combination of HF3 and HF2 has significance, it is recom-
mended that the HF3 and HF2 bits be read twice and checked for consensus.
7.4.17.4 Writing the Host Vector Register
The host processor programmer should change the Host Vector register only when the Host Command bit
(HC) is cleared. Clearing HC is a DSP96002 HI task and should not be done by the host programmer. This
guarantees that the DSP96002 interrupt control logic will receive a stable vector.