Motorola DSP96002 - Manual (Page 731)

C-8 DSP96002 USER’S MANUAL MOTOROLA
result of a floating point operation (nonzero result with true exponent smaller than the minimum
exponent, see Figure C-6) and (2) loss of accuracy is detected (delivered result differs from
what would have been computed if the exponent range was unbounded – i. e., cannot be ac-
curately represented as a denormalized number due to an insufficient number of bits or round-
off errors). Consider the case of floating point multiplication as an example. Let the first SP
source operand have a mantissa of 1.01, with biased exponent e
min
=1 (unbiased exponent of
-126) and the second SP source operand have a mantissa of 1.0 with a biased exponent of 60
(unbiased exponent of -67). The result of a multiplication with infinite precision arithmetic would
be a mantissa of 1.01 with actual (unbiased) exponent of -193 (=-126-67). Since this exponent
is smaller than the smallest exponent possible in SP, the number is tiny, and since the number
is so tiny that it cannot be accurately represented as a denormalized number (a mantissa hav-
ing 68 bits would be required), loss of accuracy also occurs, therefore an underflow will be sig-
naled. The delivered SP result would be a SP zero, and the underflow flag would be set. Note
that the SEP format can accommodate this exponent, and thus the result of an SEP operation
would not signal the underflow exception. In that case, the correct result is delivered. If the first
operand of the SP multiplication has the same value as before, but the second operand has a
biased exponent of 104 (actual exponent of -23), the result of an infinite-precision multiplication
has a mantissa of 1.01 and an actual exponent of -149. The SP result consists of a denormal-
ized number (i.e., tiny) with a mantissa of 0.00000000000000000000001 and biased exponent
of 0. Note that the denormalization process results in loss of accuracy, and therefore the the
underflow flag will be set. Finally, if the second source operand has a biased exponent of 120
(actual exponent of -7), then the resulting mantissa with infinite precision would be 1.01 as be-
fore, with an actual exponent of -133. The SP result is again denormalized (tiny) with a mantissa
of 0.000000101 and a biased exponent equal to 0. Note that there is no loss in accuracy due
to the normalization (no lost significant bits), and thus the underflow flag will not be set. The
delivered result is the correct SP denormalized number.
5. Inexact: The inexact exception is signaled if the delivered result differs from what would have
been obtained with infinite-precision arithmetic. For instance, the examples of underflow shown
above deliver numerically inexact results, and thus set the inexact flag. Another example is the
case where floating point numbers are rounded up or down.
C.1.5 Data ALU Block Diagram
The block diagram of the data ALU is shown in Figure C-8. The data ALU consists of four main parts:
1. Register file and automatic conversion unit: All operations in the data ALU are register-based
– operands as well as results of data ALU operations are read from and written to registers. A
register file consisting of ten 96-bit registers are available for storage of floating-point numbers.
An automatic conversion unit converts the floating point storage format in memory to the inter-
nal DP format when moving operands and/or results from/to memory.
2. Multiply unit: A full IEEE floating-point multiply unit, delivering either a SP or SEP result in one
instruction cycle.
3. Adder/Subtracter unit: A full IEEE floating-point adder/subtracter unit, which can deliver the
sum as well as the difference of two operands in the same instruction cycle, to either SP or SEP.
4. Special function unit: A special function unit provides various logic functions, as well as support
for divide and square root in terms of an initial seed for a fast convergent divide and square root