Motorola DSP96002 - Manual (Page 59)

5 - 6 DSP96002 USER’S MANUAL MOTOROLA
Sets of 3 Data ALU registers may be concatenated to form ten 96 bit registers which may be accessed as
single real or double real operands. Floating-point operands are always represented in an internal double
precision format, described below.
5.3.1.1 Internal floating-point Data Format
All DSP96002 internal floating-point operations are performed using single extended precision. All oper-
ands are converted to the internal double precision format when written into a Data ALU register. The in-
ternal double precision floating-point format used in the ten floating-point data registers is shown in Figure
5-4.
- S is the sign of the mantissa.
- U is the single precision unnormalized tag.
- V is the single extended precision unnormalized tag.
- Biased Exponent is a 11 bit number which is essentially the 11 bit double precision biased exponent.
- Zero are bits that are always cleared by floating-point operations and floating-point moves.
- I is the integer part of the mantissa.
- Fraction is a 52 bit field representing the fractional part of the mantissa.
Fraction S
Biased
Exponent
63 62 0
Zero Zero I U V
95 94 93 92 75 74 64 11 10
Figure 5-4. Data Format in the Floating Point Registers
When a result of an internal operations (which is a single extended precision number in the DSP96002) is
written into a Data ALU register or when writing single or double precision numbers represented in one of
the memory data formats to a Data ALU register as a result of a MOVE operation, automatic format con-
version to the internal double precision representation is performed. Thus, mixed mode arithmetic is im-
plicitly supported.
Since the DSP96002 implements single extended precision internal calculations, the Fraction part in the
register may contain actually only 31 significand bits for single extended precision results or 23 significand
bits for single precision results. However, if a double precision MOVE is performed, a 52 bit fraction will be
written into the register but, if the same register is used as a floating-point operand, only the 31 most sig-
nificand bits of the fraction will actually be used while the remaining bits are ignored by the Data ALU, re-
sulting in a truncation error toward zero. Therefore, for future compatibility, only single extended precision
data should be moved with the double precision data moves.
5.3.1.2 Internal Double Precision Format Summary
Field Size (in bits):
s = Sign ............... 1