Motorola DSP96002 - Manual (Page 784)

2 MOTOROLA
Integer Mode
The integer performance on the DSP96002 has been doubled with the introduction of the
Integer Mode (IM). The Integer Mode of operation significantly improves the performance
of integer algorithms and supports four new parallel arithmetic operations:
• integer signed multiply and add (MPYS//ADD)
• integer signed multiply and subtract (MPYS//SUB)
• integer unsigned multiply and add (MPYU//ADD)
• integer unsigned multiply and subtract (MPYU//SUB)
Single Precision Mode
The newly added Single Precision Mode (SPM) of operation improves the efficiency of the
Data ALU register file. This new operating mode gives the user access to two Data-ALU
register files: a 10 floating-point register file (d0.h..d9.h, d0.m..d9.m) and a 10 integer reg-
ister file (d0.l..d9.l). If the program uses only single-precision MOVE operations and float-
ing-point operations that yield single-precision results, then the two register files are
completely decoupled - thus effectively
doubling the amount of registers available to the
data ALU.
OnCE Enhancement
The support for development and debugging of multiprocessor systems has been
improved by the addition of a new OnCE
1
feature that permits simultaneous start of the
program execution for any number of processors, regardless of the code they are exe-
cuting. Different processors may be stopped at different points in the code they are exe-
cuting, and then their activity may be restarted synchronously and simultaneously.
Timer/Event Counter Modules
This addendum also describes the two identical and independent timer/event counter
modules newly featured on the DSP96002. The timers can use internal or external clock-
ing and can interrupt the processor after a number of events (clocks) specified by a user
program, or it can signal an external device after counting internal events. Figure 1 shows
the DSP96002 block diagram revised to include the timers.
New aWR and bWR (Write Strobe) Pins
The DSP96002 features two new outputs, aW/R and bW/R, which support a glueless in-
terface to external SRAMs. They are active-low when the DSP96002 is the bus master,
and three-stated when the DSP96002 is not the bus master. They are asserted during ex-
ternal memory write cycles to indicate that the address lines A0-A32, S1, S0, BS, BL, and
R/W are stable. The output data goes to the data bus after WR is asserted. WR is three-
1. OnCE is a trademark of Motorola Inc.