Motorola DSP96002 User Manual
Page 132
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DSP96002 USER’S MANUAL
MOTOROLA
7.5.3 DMA Control/Status Register (DCS)
The DMA Control/Status Register (DCS) is a 32-bit read/write register that controls the DMA operation.
Each bit is described in the following paragraphs.
DMA Source Modifier Register
DSM1
addr X:$FFFFFFD7
DMA Source Address Register
DSR1
addr X:$FFFFFFD6
DMA Source Offset Register
DSN1
addr X:$FFFFFFD5
DMA Destination Modifier Register
DDM1
addr X:$FFFFFFD3
DMA Destination Address Register
DDR1
addr X:$FFFFFFD2
DMA Destination Offset Register
DDN1
addr X:$FFFFFFD1
DMA Counter
DCO1
addr X:$FFFFFFD4
31 30 29 28 27 26 25 24 DMA Control/Status Register
DCS1
DE DIE * DTD * DTM1 DTM0 DMAP addr X:$FFFFFFD0
23 22 21 20 19 18 17 16
DCP * * * * * * *
15 14 13 12 11 10 9 8
* M6 M5 M4 M3 M2 M1 M0
7 6 5 4 3 2 1 0
* * DSS2 DSS1 DSS0 DDS2 DDS1 DDS0
Figure 7-26. DMA Controller Programming Model - Channel 1
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