Motorola DSP96002 - Manual (Page 68)

MOTOROLA DSP96002 USER’S MANUAL 5 - 15
5.7.2 Address Register Indirect Modes
The effective address in the instruction specifies the address register Rn and the address calculation to be
performed. These addressing modes specify that the operand(s) is in memory and provide the specific
address of the operand(s). When an address register is used to point to a memory location, the addressing
mode is called address register indirect. The term indirect is used because the operand is not the address
register itself, but the contents of the memory location pointed to by the address register. A portion of the
data bus movement field in the instruction specifies the memory reference to be performed. The type of
address arithmetic used is specified by the address modifier register Mn.
5.7.2.1 No Update (Rn)
The address of the operand is in the address register Rn. The contents of the Rn register are unchanged.
The Mn and Nn registers are ignored. This reference is classified as a memory reference.
5.7.2.2 Postincrement by 1 (Rn)+
The address of the operand is in the address register Rn. After the operand address is used, it is incre-
mented by 1 and stored in the same address register. The type of arithmetic used to increment Rn is de-
termined by Mn. The Nn register is ignored. This reference is classified as a memory reference.
5.7.2.3 Postdecrement by 1 (Rn)-
The address of the operand is in the address register Rn. After the operand address is used, it is decre-
mented by 1 and stored in the same address register. The type of arithmetic used to increment Rn is de-
termined by Mn. The Nn register is ignored. This reference is classified as a memory reference.
5.7.2.4 Postincrement by Offset Nn (Rn)+Nn
The address of the operand is in the address register Rn. After the operand address is used, it is incre-
mented (added) by the contents of the Nn register and stored in the same address register. The content
of Nn is treated as a 2’s complement number and can therefore be interpreted as signed or unsigned (see
Section 5.8.1). The contents of the Nn register are unchanged. The type of arithmetic used to increment
Rn is determined by Mn. This reference is classified as a memory reference.
5.7.2.5 Postdecrement by Offset Nn (Rn)-Nn
The address of the operand is in the address register Rn. After the operand address is used, it is decre-
mented (subtracted) by the contents of the Nn register and stored in the same address register. The con-
tent of Nn is treated as a 2’s complement number and can therefore be interpreted as signed or unsigned
(see Section 5.8.1). The contents of the Nn register are unchanged. The type of arithmetic used to incre-
ment Rn is determined by Mn. This reference is classified as a memory reference.
5.7.2.6 Indexed by Offset Nn (Rn+Nn)
The address of the operand is the sum of the contents of the address register Rn and the contents of the
address offset register Nn. The content of Nn is treated as a 2’s complement number and can therefore
be interpreted as signed or unsigned (see Section 5.8.1). The contents of the Rn and Nn registers are un-