Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 111)

upi_mode_en[3:0] Input
40GBASE-KR4 microprocessor
interface. These signals are
present only in 40GBASE-KR4
variations for which you turn on
Enable microprocessor
interface. All 40GBASE-KR4
variations are in Duplex mode.
upi_adj[7:0] Input
upi_inc[3:0] Input
upi_dec[3:0] Input
upi_pre[3:0] Input
upi_init[3:0] Input
upi_st_bert[3:0] Input
upi_train_err[3:0] Input
upi_lock_err[3:0] Input
upi_rx_trained[3:0] Input
upo_enable[3:0] Output
upo_frame_lock[3:0] Output
upo_cm_done[3:0] Output
upo_bert_done[3:0] Output
upo_ber_cnt[4*<bcw>-1:0]
(width varies with <bcw> = BER
counter width)
Output
upo_ber_max[3:0] Output
upo_coef_max[3:0] Output
3-64 Signals of MAC and PHY Variations Without Adapters
UG-01088
2014.12.15
Altera Corporation Functional Description
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