Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 17)

Module ALMs Logic Registers
Memory
M20K
• alt_e100_phy_
pcs:phy_pcs
23000 41700 0
• • alt_e100_pcs_
rx:pcs_rx
13600 26300 0
• • alt_e100_pcs_
tx:pcs_tx
8700 13700 0
• • alt_e100_phy_
csr:phy_csr
700 1700 0
• alt_e100_phy_pma_
sv:pma
500 800 0
Table 1-7: 100GbE IP Core FPGA Resource Utilization in Stratix IV Devices
Lists the resources and expected performance for selected variations of the 100GbE IP cores in a Stratix IV device.
The results were obtained using the Quartus II software v13.1 for a Stratix IV EP4S100G5F45C2 device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
Module ALMs Logic Registers
Memory
M9K
MAC&PHY with
Avalon-ST client
interface without
statistics counters
60300 96000 29
MAC&PHY with
Avalon-ST client
interface and with
statistics counters
65200 102400 29
MAC with Avalon-ST
client interface
without statistics
counters
30700 48600 29
1-14 Resource Utilization for 100GbE IP Cores
UG-01088
2014.12.15
Altera Corporation About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
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