Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 36)

• ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices
Chapter in volume 3: Transceiver Configuration Guide of the Stratix IV Device Handbook. Describes
the ALTGX_RECONFIG megafunction, which configures a transceiver reconfiguration block for a
Stratix IV device.
Placement Settings for the 40-100GbE IP Core
The Quartus II software provides the options to specify design partitions and LogicLock ™ regions for
incremental compilation, to control placement on the device. To achieve timing closure for your design,
you might need to provide floorplan guidelines using one or both of these features.
The appropriate floorplan is always design-specific, and depends on your full design.
Related Information
Quartus II Handbook Volume 2: Design Implementation and Optimization
Describes incremental compilation, design partitions, and LogicLock regions.
40-100GbE IP Core Testbenches
Altera provides a testbench and an example design with most variations of the 40-100GbE IP core. The
testbench is available for simulation of your IP core, and the example design targets a C2 speed grade
device and can be run on hardware. You can run the testbench to observe the IP core behavior on the
various interfaces in simulation.
Altera offers testbenches for the following configurations:
• Non-40GBASE-KR4 IP core variations that have all of the following properties:
• Includes both MAC and PHY components (Core options has the value of MAC & PHY)
• Full duplex (Duplex mode has the value of Full Duplex)
• 40GBASE-KR4 IP core variations that have all of the following properties:
• Includes both MAC and PHY components (Core options has the value of MAC & PHY)
• With adapters (MAC client interface has the value of Avalon-ST interface)
• Without Synchronous Ethernet support (Enable SyncE support is turned off)
• Without the link training microprocessor interface (Enable microprocessor interface is turned off)
• RX equalization enabled (Enable RX equalization is turned on)
When you generate your IP core and turn on Generate example design, the Quartus II software generates
the testbench and example design for your variation. If your IP core variation does not meet the criteria
for a testbench, the generation process does not create a testbench. Turning on Generate example design
does not force the software to generate a testbench if none is defined for your variation.
MAC-only, PHY-only, TX-only, and RX-only IP core variations do not generate an example design and
testbench. 40GBASE-KR4 IP core variations with the custom streaming interface, without RX equaliza‐
tion enabled, with Synchronous Ethernet support, or with the link training microprocessor interface, do
not generate a testbench. (However, 40GBASE-KR4 IP core variations that conform to all the require‐
ments with the exception of the requirement of adapters, do generate an example design that runs in
hardware).
Conceptually, the testbenches for the 40-100GbE IP cores with adapters (IP cores with an Avalon-ST
client interface) and the testbenches for the 40-100GbE IP cores without adapters (IP cores with the
2-14 Placement Settings for the 40-100GbE IP Core
UG-01088
2014.12.15
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