Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 173
Address Map Changes for the 40-100GbE IP
Core v12.0 Release
B
2014.12.15
UG-01088
Table B-1: Address Map and Register Name Changes for the 40-100GbE IP Core v12.0 Release
For improved organization and clarity, version 12.0 of the 40- and 100-Gbps MAC and PHY MegaCore Function
revised the address map and renamed a few registers. This table lists the address map changes in the 12.0 software
release. These address map changes apply to Stratix IV and Stratix V devices.
Current 40/100GbE
Address
Current Name
Previous Address
Previous Name
0x017
PCS_HW_ERR
HW_ERR
0x018
BER_MONITOR
Reserved
0x019
TEST_MODE
Reserved
0x01a
TEST_PATTERN_
COUNTER
Reserved
0x01b
Enable Link Fault
sequence
Reserved
0x01d
PHY reset
Reserved
0x120
MAC_HW_ERR
Reserved
0x121
MAC Reset
Reserved
0x122
MAC/RS link fault
sequence configuration
Reserved
0x123
CRC_CONFIG
Reserved
0x162-0x17f
Reserved
0x160-0x017f
DST_ADR
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