100gbe ip core registers, 100gbe ip core registers -79 – Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 126
Table 3-25: 40-100GbE Example Design Registers
Lists the memory mapped registers for the 40-100GbE IP core example design.
Word Offset
Register Category
0x400–0x403
PMD registers
0x404–0xF0F
Reserved
0x410–0x413
MDIO registers
0x414–0x41F
Reserved
0x420–0x423
2-wire serial interface registers
Related Information
•
•
on page 3-84
•
Link Fault Signaling Registers
•
•
on page 3-91
•
•
•
MAC Configuration and Filter Registers
•
on page 3-104
•
•
on page 3-116
•
•
2-Wire Serial Interface Registers
on page 3-118
•
The CAUI–4 variations of the 40-100GbE IP core use the Low Latency PHY IP core registers at
internal offsets 0x000-0x1FF (at IP core register map offsets 0x800–0xFFF), and the non-CAUI–4
Arria V GZ and Stratix V variations use the Low Latency PHY IP core registers at internal offsets
0x040–0x07F (at IP core register map offsets 0x040–0x07F). Information about this PHY IP core,
including loopback configuration, is available in the Low Latency PHY IP Core chapter of the Altera
Transceiver PHY IP Core User Guide..
The 40GBASE-KR4 variations of the 40-100GbE IP core use the 10GBASE-KR PHY IP core PHY
registers at internal offsets 0xB0–0xFF (at IP core register map offsets 0xB0–0xFF). Information about
this PHY IP core, including register descriptions, is available in the Backplane Ethernet 10GBASE-KR
PHY IP Core with FEC Option chapter of the Altera Transceiver PHY IP Core User Guide..
40-100GbE IP Core Registers
The following sections describe the registers included in the 40-100GbE IP core.
Transceiver PHY Control and Status Registers
on page 3-80
UG-01088
2014.12.15
40-100GbE IP Core Registers
3-79
Functional Description
Altera Corporation