Zilog Z16C30 User Manual
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Z16C30 USC
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U
SER
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M
ANUAL
Z
ILOG
UM97USC0100
5.23 HANDLING OVERRUNS AND UNDERRUNS
In general, both the Tx Underrun condition in the TCSR and
the Rx Overrun condition in the RCSR should be enabled
and armed for interrupt. While the USC can handle most
things that can arise in normal operation in a fairly auto-
matic fashion, these two conditions represent a break-
down in the relationship between the USC and its environ-
ment, namely insufficient servicing of DMA requests or
Data interrupt requests. Software should respond to these
conditions quickly to minimize further loss of received data
and to prevent erroneous transmission.
5.23.1 Tx Underruns
All revisions of the USC will deal with a Transmit Underrun
condition in synchronous modes by (1) concluding the
current frame or message as specified in the TxSubMode
field of the Channel Mode Register (CMR), which may have
been set from a Transmit Control Block, and (2) setting the
TxUnder bit in the TCSR.
But if a Tx DMA channel then (finally) responds to the
Transmitter’s DMA Request and puts more data in the
TxFIFO, before software can respond to the Underrun
condition, the Transmitter can thereafter begin sending a
new frame, typically starting with data that was meant to be
in the middle of a frame.
If an application is subject to Tx Underruns and has
response latency to the Underrun condition that allows
such a subsequent frame to be started out onto the serial
link, for USC'S manufactured before June 1993, the only
practical way to avoid this behavior is to set the Wait2Send
bit (TICR2) and have software issue a Send Frame/Mes-
sage command to allow each Tx frame out onto the link.
This procedure may degrade transmit performance.
For USCs manufactured after June of 1993, software can
avoid both the problem and the performance degradation
associated with the Wait2Send workaround, by setting the
UnderWait
bit in the Transmit Command/Status Register
(TCSR11), which was Reserved in previous revisions.
When UnderWait is set, the USC’s Transmitter will wait after
dealing with a Transmit Underrun condition, sending the
Idle condition specified in the TCSR, until software recog-
nizes the Underrun condition and deals with it. The recom-
mended software response is:
1.
Stop the Tx DMA channel if one is used
2.
Write the “Purge Tx FIFO” command to the CCAR
3.
Reprogram the Tx DMA channel (if used) to the start of
the frame in which the underrun occurred,
4.
Start the Tx DMA channel (if used),
5.
Write the “Send Frame/Message” command (plus the
UnderWait bit) to the TCSR. This command releases
the interlock caused by the underrun condition with
UnderWait=1.
6.
If the Underrun condition is armed for interrupt, write a
1 to TCSR1 to clear the status bit.
7.
If Underrun and other conditions are armed to cause
Transmit Status interrupts, clear all the IA bits in the
TICR and then restore those that should be Armed.
When 32-bit Transmit Control Blocks are used, setting
UnderWait to 1 has a further effect that helps minimize the
occurrence of Tx Underrun conditions. When the TxCtrlBlk
field (CCSR15-14) is 10 and UnderWait (TCSR11) is 1, the
Transmitter will delay starting to send a frame until either
the TxFIFO is full or an entire Tx frame has been placed in
the TxFIFO.
Using Underwait with 32-bit TCBs helps minimize Tx
underruns if an Rx DMA channel has pre-emptive priority
over a Tx DMA channel, and it seizes control of the bus just
after the Tx DMA channel has placed the first one or two
characters of a new Tx frame in the TxFIFO.
5.23.2 Rx Overruns
If software or the Rx DMA channel doesn’t read data from
the RDR/RxFIFO often enough, the 32-character Rx FIFO
may fill-up. If another character arrives while the RxFIFO is
full, the Receiver saves this character in a holding register
between the Rx shift register and the RxFIFO. When the Rx
DMA gets around to reading from the RxFIFO again, the
Receiver places this “overrun character” in the RxFIFO
with a status bit that accompanies it through the FIFO.
When the Rx DMA channel stores the overrun character in
memory, the USC sets the RxOver bit in the RCSR and
requests an interrupt if the RxOver IA bit in the RICR and
the RSIE and MIE bits in the ICR are all 1.
Once an overflow has occurred, the Receiver doesn’t put
any more received data in the RxFIFO (even if the external
processor/arbiter grants the bus and the Rx DMA channel
stores some or all of the data from the FIFO into memory)
until software responds. The proper software response is
to:
1.
Stop the Rx DMA channel (if used)
2.
Write an “Enter Hunt Mode” command to the RCSR
UM009402-0201