Zilog Z16C30 User Manual

Page 25

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1-12

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

1.6 DEVICE STRUCTURE

Figure 1-1 shows the basic structure of the USC. The Bus
Interface module stands between the external bus pins
and an on-chip 16-bit data bus that interconnects the other
functional modules. It includes several flexible bus inter-
facing options that are controlled by the Bus Configuration
Register (BCR). The BCR is automatically the destination
of the first write cycle from the host processor to the USC
after a Reset. After that it is no longer accessible to the host
software.

1.6.1 The Transmit Data Path

Either the host processor or an external DMA channel can
write transmit data into a channel’s Transmit First-In, First-
Out (FIFO) memory. At any time, a Transmit FIFO can be
empty or can contain from 1 to 32 characters to be
transmitted. Characters written into the TxFIFO become
available to the Transmitter in the order in which they were
written.

While the host processor can itself write data into the
Transmit FIFOs, it’s more efficient to use external Transmit
DMA channels to fetch the data. The host can program a
USC channel so that its Transmitter will trigger its DMA
controller to fill its FIFO at varying degrees of FIFO “emp-
tiness”. Selecting this point involves balancing the prob-
ability and consequences of “underrunning” the transmit-
ter, against the overhead for the DMA channel to acquire
control of the host bus more often.

The serial Transmitters take characters from the Transmit
FIFOs and convert them to serial data on the TxD pins.
While this function is conceptually simple, the USC sup-
ports many complex serial protocols, which increases the
complexity of the Transmitters dramatically. Depending on
the serial mode selected, the Transmitters may do any of
the following in addition to parallel-serial conversion: start,
stop, and parity bit generation, calculating and sending
CRCs, automatic generation of opening and closing flags,
encoding the serial data into any of several formats that
guarantee transitions and carry clocking with the data,
and/or controlling transmission based on the CTS pin.

1.6.2 The Receive Data Path

In general, the functions of the Receivers are the inverse of
those of the Transmitters: they monitor the serial data on
the RxD pin, organize it according to the serial mode
selected by the software, and convert the data to parallel
characters that they place in the Receive FIFOs. Again,
there is more to the process than just serial-parallel con-
version. Depending on the serial mode the Receivers may

have to detect and synchronize start bits, check parity and
stop bits, calculate and check CRCs, detect flag, abort
and idle sequences, recognize control characters includ-
ing transparency considerations, decode the serial data
and clock extraction using any of several encoding
schemes, and/or enable and disable reception based on
the DCD input pin. The Receivers’ checking functions
generate several status bits associated with each charac-
ter, that accompany the characters through the Receive
FIFOs.

The Receive FIFOs can hold up to 32 characters and their
associated status bits. As the receivers write entries into
their FIFOs, the entries become available to either the host
processor or external Receive DMA channels. As on the
transmit side, the Receive FIFOs include detection logic
for various degrees of “fullness”. Separate thresholds
control the point at which a channel starts requesting its
DMA channel starts to refill its FIFO, and at which a channel
requests an interrupt. Besides the main Receive FIFOs,
each channel has a 4-entry RCC FIFO that can hold values
indicating the length of up to four received frames.

While the host processor can access data from the Re-
ceive FIFOs, it’s more efficient to use external Receive
DMA channels to transfer the data directly into buffer areas
in memory. The USC can provide the status (and optionally
the RCC value at the end) of each frame in the serial data
stream, after the last character of the frame.

1.6.3 Clocking

Each channel includes a Serial Clocking Logic section that
creates the clocking signals for the channel’s Transmitter
and Receiver. Software can program the clocking logic to
do this in various ways based on one or two external
clock(s) for each channel. Each channel also includes a
Digital Phase Locked Loop (DPLL) circuit that can recover
clocking from encoded data on RxD.

1.6.4 Interrupts

There’s also an Interrupt Control section in each channel,
that gathers the various “request” lines from the Transmit-
ter and Receiver, and takes care of requesting host inter-
rupts and responding to host interrupt-acknowledge cycles
or to software equivalents. Interrupt operation depends on
the data written to the Bus Configuration Register and on
several registers in the Receiver and Transmitter. There
are a separate set of interrupt pins for each channel so that
external logic can control their relative priority.

UM009402-0201

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