1 detailed status in the tcsr, 18 status reporting (continued) – Zilog Z16C30 User Manual

Page 95

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5-28

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.18.1 Detailed Status in the TCSR

PreSent:

The Transmitter sets this bit (TCSR7) in a syn-

chronous mode, when it has finished sending the Pre-
amble specified in the TxPreL and TxPrePat fields of the
Channel Control Register (CCR). A channel can request an
interrupt when this bit goes from 0 to 1 if the PreSent IA bit
in the Transmit Interrupt Control Register (TICR7) is 1.
Software must write a 1 to PreSent to unlatch and clear it,
and to allow further interrupts if TICR7 is 1; writing a 0 to
PreSent has no effect. See the later section 'Between
Frames, Messages, or Characters' for more information on
Preambles.

IdleSent:

The Transmitter sets this bit (TCSR6) in any

mode, when it has finished sending “one unit” of the Idle
line condition specified in the TxIdle field in the MSByte of
this TCSR. If the Idle condition is Syncs or Flags as
described later in 'Between Frames, Messages, or Char-
acters', the unit is one character or sequence and the flag
and interrupt can recur for each one sent. For any other Idle
condition, the Transmitter sets the flag and interrupt only
once, when it has sent the first bit of the condition. The
channel can request an interrupt when this bit goes from 0
to 1 if the IdleSent IA bit in the Transmit Interrupt Control
Register (TICR6) is 1. Software must write a 1 to IdleSent
to unlatch and clear it, and to allow further interrupts if
TICR6 is 1; writing a 0 to IdleSent has no effect.

AbortSent:

The Transmitter sets this bit (TCSR5) in

HDLC/SDLC or HDLC/SDLC Loop mode, when it has
finished sending an Abort sequence. A channel can re-
quest an interrupt when this bit goes from 0 to 1 if the
AbortSent IA bit in the Transmit Interrupt Control Register
(TICR5) is 1. Software must write a 1 to AbortSent to unlatch
and clear it, and to allow further interrupts if TICR5 is 1;
writing a 0 to AbortSent has no effect. See the earlier
sections 'HDLC/SDLC Mode' and 'HDLC/SDLC Loop Mode'
for more information on Abort sequences.

EOF/EOM Sent:

The Transmitter sets this bit (TCSR4) in a

synchronous mode, when it has finished sending a closing
Flag or Sync sequence. A channel can request an interrupt
when this bit goes from 0 to 1 if the EOF/EOM Sent IA bit in
the Transmit Interrupt Control Register (TICR4) is 1. Soft-
ware must write a 1 to EOF/EOM Sent to unlatch and clear
it, and to allow further interrupts if TICR4 is 1; writing a 0 has
no effect. See the later section 'Between Frames, Mes-
sages, or Characters' for more information on closing
Flags and Syncs.

CRCSent:

The Transmitter sets this bit (TCSR3) in a

synchronous mode, when it has finished sending a Cyclic
Redundancy Check sequence. A channel can request an
interrupt when this bit goes from 0 to 1 if the CRC Sent IA
bit in the Transmit Interrupt Control Register (TICR3) is 1.
Software must write a 1 to CRCSent to unlatch and clear it,
and to allow further interrupts if TICR3 is 1; writing a 0 to
CRCSent has no effect. See the section 'Cyclic Redun-
dancy Checking' for more information on CRC’s.

AllSent:

This read-only bit (TCSR2) is 0 in asynchronous

modes, while the Transmitter is sending a character.
Software can use this bit to figure out when the last
character of an async transmission has made it out onto
TxD, before changing the mode of the Transmitter.

TxUnder:

The Transmitter sets this bit (TCSR1) in any

mode, when it needs another character to send but the
TxFIFO is empty. It does this even in asynchronous modes.
A channel can request an interrupt when this bit goes from
0 to 1 if the TxUnder IA bit in the Transmit Interrupt Control
Register (TICR1) is 1. The Transmitter sets TxUnder one or
two clocks before the current character is completely sent
on TxD. See 'Handling Overruns and Underruns' later in
this chapter for further details on how to handle this
condition.

TxEmpty:

This read-only bit (TCSR0) is 1 when the TxFIFO

is empty, and 0 when it contains one or more characters.

5.18 STATUS REPORTING

(Continued)

TCmd

Under

Wait

Txidle

Pre

Sent

Idle

Sent

Abort

Sent

EOF/
EOM

Sent

CRC

Sent

All

Sent

Under

Empty

Figure 5-11. The Transmit Command/Status Register (TCSR)

UM009402-0201

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