Zilog Z16C30 - Manual (Page 42)

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Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
2.9.7 Register Read and Write Cycles (Continued)
ADnn
A//B, D//C
/CS
/SITACK
/PITACK, /RD,(/WR or /DS),
DMA Acknowledge signals
/AS
R//W
(Required with /DS, not with /WR.)
/DS or /WR
Wait Mode
/WAIT//RDY
Address Data
Acknowledge Mode
Figure 2-11. A Register Write Cycle with Multiplexed Addresses and Data
UM009402-0201