Zilog Z16C30 User Manual

Page 58

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4-9

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

In the Bi-phase-Level and Differential Bi-phase-Level
encodings, there is always a transition at the midpoint of
each active data bit, and there may or may not be transi-
tions at the boundaries between bit cells. The DPLL gen-
erates clocks as for Bi-phase-Mark and -Space, but must
know the difference between those modes and these to do

so. The Receiver determines each data bit from the state
of RxD at falling edges of RxCLK and checks for “missing
clocks” around rising edges. The Transmitter may or may
not change TxD at falling edges of TxCLK, depending on
the current data bit. It always inverts TxD at rising edges.

The DPLL does not include logic to track the clock fre-
quency of the remote end in a long-term manner. Rather it
is a counter that is affected by transitions on RxD, and uses
the reference clock to make bit clocking that is more or less
synchronized to these transitions. Figure 4-5 shows the
USC’s Channel Command/Status Register. Its

DPLLEdge

field (CCSR9-8) provides further control over DPLL opera-
tion. For most applications, this field should be 00, in which
case the DPLL resynchronizes its counter on both rising
and falling edges on RxD.

For NRZ applications in which one kind of edge is signifi-
cantly more precise than the other, software can program
the DPLLEdge field to 10 or 01, to make the DPLL ignore
one kind of transition. One example of such an application
is a serial bus with passive external pull-ups; in such a
application, falling edges are more accurate than rising
edges. If DPLLEdge is 11, the DPLL never resynchronizes
— that is, it runs freely like CTR0 and CTR1.

Because the blocking of edges by DPLLEdge affects
missing clock detection as well as resynchronization, for
Biphase operation DPLLEdge should always be pro-
grammed as 00.

In any NRZ mode, when the DPLL is in sync, it uses the
selected nominal value (8, 16, or 32 cycles of its input
clock) for counting off the next bit cell if a transition on RxD
falls near the bit cell boundary. If a transition comes early
it uses the nominal value minus 1 for the next cell, while if
a transition comes late it uses the nominal value plus one.
In /16 and /32 modes only, the DPLL uses the nominal
value plus two for the next bit cell if a transition comes very
late in a cell, and the nominal value minus two if a transition
comes very early.

In Bi-phase-Mark or Bi-phase-Space modes, when the
DPLL is in sync it ignores “data” transitions in the second
and third quarters of the bit cell, and resynchronizes to

“clock” transitions in the fourth and first quarters of the cell.
If a clock transition falls very close to the cell boundary, the
DPLL uses the nominal value (8, 16, or 32) as the length of
the next bit cell. Otherwise it uses the nominal value minus
one if a clock transition comes early, or the nominal value
plus one if a clock transition is late.

In Bi-phase-Level or Differential Bi-phase-Level modes,
when the DPLL is in sync it ignores “data” transitions in the
first and fourth quarters of the bit cell, and resynchronizes
to “clock” transitions in the second and third quarters of the
cell. If a clock transition falls close to the middle of the cell,
the DPLL uses the nominal value (8, 16, or 32) as the length
of the next bit cell. Otherwise it uses the nominal value
minus one if a clock transition comes early, or the nominal
value plus one if the clock transition is late.

In an NRZ mode, if there’s no transition in a bit cell the DPLL
uses the nominal value (8, 16, or 32 clocks) as the length
of the next bit cell. It also does this in Biphase modes, if
there is no clock transition in a bit cell when the DPLL is in
sync. In particular, in these cases the DPLL doesn’t re-
apply a correction from a previous bit cell.

In Bi-phase modes, the

CVOK

bit in the Hardware Control

Register (HCR12) controls whether the Receiver flags a
single code violation as an error. If CVOK=0, it sets the
DPLL1Miss bit for a single code violation as described
below. If CVOK=1, it doesn’t report a single code violation
in DPLL1Miss; use this setting when the protocol includes
single code violations as normal occurrences, as in the
1533B mode that’s described in Chapter 5. Regardless of
CVOK, code violations in two consecutive bit cells set the
DPLL2Miss and DPLLDSync L/U bits and de-synchronize
the DPLL.

Figure 4-5. The Channel Command/Status Register (CCSR)

RCCF

Ovflo

RCCF

Avail

Clear

RCCF

DPLL

Sync

DPLL

2Miss

DPLL

1Miss

DPLLEdge

Loop

Send

Loop

Rsrvd

TxResidue

/TxACK /RxACK

UM009402-0201

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