Zilog Z16C30 User Manual
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5.5.2 Character Length
(Continued)
When RxLength is less than eight in synchronous modes
including HDLC/SDLC, the Receiver fills out the more
significant bits of each byte with the last received bit (the
parity bit if one is used), except in three cases:
1.
In Monosync and Bisync modes, when CMR4 is 1 so
that sync characters are 8 or 16 bits long, but data
characters contain less than 8 bits, each data charac-
ter is left-justified in its byte.
2.
In HDLC/SDLC mode, when CMR5-4 are non-zero so
that address and control characters are 8 bits long but
subsequent characters are less than 8 bits long, each
subsequent character is left-justified in its byte.
3.
In HDLC/SDLC mode, if the frame doesn’t end on a
character boundary, its final data bits are left-justified
within the (right-justified) number of bits specified by
RxLength, unless case 2 also applies, in which case
they’re left-justified in the last byte. (The number of bits
in the last character of each HDLC/SDLC frame is
always indicated in the RxResidue field of the RCSR.)
In any of these three cases of left-justified data, the less-
significant bits are left over from the previous character.
If software enables parity checking in an asynchronous
mode, the Transmitter and Receiver handle the parity bit
as an additional bit after the number of bits defined by
TxLength and RxLength. If software selects parity check-
ing in a synchronous mode, the Transmitter and Receiver
handle the parity bit as the last of the number of bits
specified by TxLength and RxLength.
Software should reprogram RxLength only while the Re-
ceiver is either disabled, in Hunt state in a synchronous
mode, or between characters in an asynchronous mode.
Software can reprogram TxLength at any time, but a new
length takes effect only when the Transmitter loads the
next character into its shift register.
5.5.3 Parity, CRC, Serial Encoding
A later section of this chapter, 'Parity Checking', discusses
how bits 7-5 of both the TMR and RMR control parity
checking.
Similarly, a later section of this chapter, 'Cyclic Redun-
dancy Checking', describes how bits 12-8 of the TMR and
RMR control CRC checking.
The
TxEncode
and
RxDecode
fields (TMR15-13 and
RMR15-13) specify how the Transmitter encodes serial
data on the TxD pin and how the Receiver decodes it on the
RxD pin. See Chapter 4 for a full description of the following
encodings:
xMR15-13
Data Format
000
NRZ
001
NRZB
010
NRZI-Mark
011
NRZI-Space
100
Bi-phase-Mark
101
Bi-phase-Space
110
Bi-phase-Level
111
Differential Bi-phase-Level
UM009402-0201