Sundance Spas ST201 - Manual (Page 105)

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Sundance Technology ST201 PRELIMINARY draft 2
CACHELINESIZE
Class....................PCI Configuration Registers, Configuration
Base Address ......PCI device configuration header start
Address Offset .....0x0c
Access Mode .......Read/Write
Width ...................8 bits
BIT BIT NAME BIT DESCRIPTION
7..0 CacheLineSize The system BIOS writes the system’s cache line size into this register.
The adapter uses this to optimize PCI bus master operation (choosing
the best memory command, etc.). The value in CacheLineSize repre-
sents the number of dwords in a cache. CacheLineSize only supports
powers of two from 4 to 64 (giving a range of 16 to 256 bytes). An
unsupported value is treated the same as zero.