Sundance Spas ST201 - Manual (Page 64)

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Sundance Technology ST201 PRELIMINARY draft 2
INTENABLE
Class....................I/O Registers, Interrupt
Base Address ......IoBaseAddress register value
Address Offset .....0x4c
Access Mode .......Read/Write
Width ...................16 bits
Enables individual interrupts as specified in the IntStatus register. Setting a bit in IntEnable will allow the
specific source to generate an interrupt on the PCI bus. IntEnable is cleared upon reset. IntEnable is also
cleared by a read of IntStatusAck.
BIT BIT NAME BIT DESCRIPTION
0 Unused This bit will be ignored.
1 EnHostError Enables the HostError interrupt.
2 EnTxComplete Enables the TxComplete interrupt.
3 EnMACControl-
Frame Enables the MACControlFrame interrupt.
4 EnRxComplete Enables the RxComplete interrupt.
5 EnRxEarly Enables the RxEarly interrupt.
6 EnInRequested Enables the InRequested interrupt.
7 EnUpdateStats Enables the UpdateStats interrupt.
8 EnLinkEvent Enables the LinkEvent interrupt.
9 EnTxDMACom-
plete Enables the TxDMAComplete interrupt.
10 EnRxDMACom-
plete Enables the RxDMAComplete interrupt.
15..11 Unused These bits bill be ignored.