Sundance Spas ST201 - Manual (Page 47)

47
Sundance Technology ST201 PRELIMINARY draft 2
19 DMA When set, together with GlobalReset, RxReset, or TxReset bits, will
reset RxDMA and TxDMA Logic, including: TxDMAListPtr, RxDMAL-
istPtr, TxDMAComplete TxDMAInProg RxDMAComplete and RxEarly-
Enable in DMACtrl and RxDMAStatus. When cleared, reset will not
have action on the DMA Logic. This bit is self-clearing. Setting this bit
has no meaning if the corresponding reset bits are not set.
20 FIFO When set, together with GlobalReset, RxReset, or TxReset bits, will
reset FIFO control logic, including TxStartThresh, TxReleaseThresh,
and RxEarlyThresh. When cleared, reset will not have action on the
DMA Logic. This bit is self-clearing. Setting this bit has no meaning if
the corresponding reset bits are not set.
21 Network When set, together with GlobalReset, RxReset, or TxReset bits, will
reset network interface logic, including CSMA/CD MAC core, Receive-
Mode, TxStatus, and the statistics registers. When cleared, reset will
not have action on the network logic. This bit is self-clearing. Setting
this bit has no meaning if the corresponding reset bits are not set.
22 Host When set, together with GlobalReset bit, will reset host bus interface
logic, including IntStatus, IntEnable, and Countdown. When cleared,
reset will not have action on the host bus interface logic. This bit is self-
clearing. Setting this bit has no meaning if the corresponding Global-
Reset bit is not set.
23 AutoInit When set, together with GlobalReset bit, will reset auto-initialize state
machine logic and EEPROM data is reloaded. This bit is self-clearing.
Setting this bit has no meaning if the corresponding GlobalReset bit is
not set.
24 RstOut When set, together with GlobalReset bit, will assert RSTOUT accord-
ing to RstOutPolarity. When cleared, reset will not cause any action on
RSTOUT. This bit is self-clearing. Setting this bit has no meaning if the
corresponding GlobalReset bit is not set.
25 InterruptRequest When set, the ST201 will assert IntRequested bit in the IntStatus regis-
ter. This bit is self-clearing.
26 ResetBusy When set, this bit indicates the reset is in progress. As the adapter’s
serial EEPROM may need to be read as part of the reset process, this
operation can take as long as 1 ms to complete. The ResetBusy bit
must be polled to be assured that the reset operation has completed.
31..27 Reserved Reserved for future use. Should be set to 0.
BIT BIT NAME BIT DESCRIPTION