Zilog Z08470 - Manual (Page 138)

Z80 Instruction Set UM008007-0715
126
Z80 CPU
User Manual
EX (SP), IX
Operation
IXH
↔
(SP+1), IXL
↔
(SP)
Op Code
EX
Operands
(SP), IX
Description
The low-order byte in Index Register IX is exchanged with the contents of the memory
address specified by the contents of register pair SP (Stack Pointer), and the high-order
byte of IX is exchanged with the next highest memory address (SP+1).
Condition Bits Affected
None.
Example
If Index Register IX contains 3988h , the SP register pair Contains 0100h , memory loca-
tion 0100h contains byte 90h , and memory location 0101h contains byte 48h , then the
instruction EX (SP), IX results in the IX register pair containing number 4890h , memory
location 0100h containing 88h , memory location 0101h containing 39h , and the Stack
Pointer containing 0100h .
M Cycles T States 4 MHz E.T.
6 23 (4, 4, 3, 4, 3, 5) 5.75
1 1 1 0 1 1 0 1 DD
1 1 0 1 1 0 1 0 E3