Figure 21. adding one wait state to an m1 cycle, Figure 21 is an example, Indicated in figure 22 – Zilog Z08470 User Manual
Page 36
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Hardware and Software Implementation
UM008007-0715
24
Z80 CPU
User Manual
Figure 21. Adding One Wait State to an M1 Cycle
Figure 22. Adding One Wait State to Any Memory Cycle
+5V
D
C
Q
Q
R
S
7474
+5V
D
C
Q
Q
R
S
7474
+5V
M1
CLK
WAIT
CLK
M1
WAIT
M1
T
1
T
2
T
W
T
3
T
4
+5V
D
C
Q
Q
R
S
7474
+5V
D
C
Q
Q
R
S
7474
+5V
MREQ
CLK
+5V
7400
WAIT
WAIT
MREQ
CLK
T
1
T
2
T
W
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