Zilog Z08470 - Manual (Page 306)

Z80 Instruction Set UM008007-0715
294
Z80 CPU
User Manual
Condition Bits Affected
S is set if input data is negative; otherwise, it is reset.
Z is set if input data is 0; otherwise, it is reset.
H is reset.
P/V is set if parity is even; otherwise, it is reset.
N is reset.
C is not affected.
Example
Register C contains 07h , Register B contains 10h , and byte 7Bh is available at the periph-
eral device mapped to I/O port address 07h . Upon the execution of an IN D, (C) com-
mand, the D Register contains 7Bh .