Zilog Z08470 - Manual (Page 51)

UM008007-0715 Load and Exchange
Z80 CPU
User Manual
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The Z80 instruction mnemonics consist of an op code and zero, one, or two operands.
Instructions in which the operand is implied contains no operand. Instructions that contain
only one logical operand, in which one operand is invariant (such as the Logical OR
instruction), are represented by a one-operand mnemonic. Instructions that contain two
varying operands are represented by two operand mnemonics.
Load and Exchange
Table 5 defines the op codes for all of the 8-bit load instructions implemented in the Z80
CPU. Also described in this table is the type of addressing used for each instruction. The
source of the data is found on the top horizontal row and the destination is specified in the
left column. For example, load Register C from Register B uses the op code
48h . In all of
the figures, the op code is specified in hexadecimal notation and the 48h ( 0100 1000
binary) code is fetched by the CPU from external memory during M1 time, decoded, and
then the register transfer is automatically performed by the CPU.
The assembly language mnemonic for this entire group is LD, followed by the destination,
followed by the source (LD DEST, SOURCE).
Several combinations of addressing modes are possible. For example, the source can use
register addressing and the destination can be registered indirect; such as load the memory
location pointed to by Register HL with the contents of the D Register. The op code for this
operation is 72. The mnemonic for this load instruction is LD (HL), D.
8 = 1000 = 8
9 = 1001 = 9
A = 1010 = 10
B = 1011 = 11
C = 1100 = 12
D = 1101 = 13
E = 1110 = 14
F = 1111 = 15
Table 4. Hex, Binary, Decimal Conversion Table (Continued)
Hex Binary Decimal
Note: